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Wafer bonding is an important process step in microsystem technologies for processing engineered substrates and for capping. Usually, the work and literature are focused on the bonding of the main wafer area. However, in recent years MEMS technologies have become more complex, with more process steps after wafer bonding. Accordingly, the wafer edge is becoming more and more important, and must be engineered. Methods for realizing this are discussed in this paper.

This work investigates the effect of varying the structural characteristics of fusion-bonded thick SOI on the quality of oxides grown during fabrication of transistors using normal CMOS processing methods. The influences of the SOI device material, handle material and bonding procedure were examined using material supplied by various SOI vendors. In addition, the incorporation of gettering sites into the SOI layer near the interface with the buried oxide, was studied using buried implanted layers of various species. We found a strong influence of both the vendor and the position of the bonding interface on the quality of the surface thermal oxides, with handle-oxidised material giving superior gate oxides to device-oxidised SOI. A large improvement in oxide quality was shown by the introduction of the implanted ions, which was strongly dependent on the species, germanium giving the largest effect. This enabled the growth of high quality gate and tunnel oxides for electronic device fabrication. IntroductionSeveral techniques have conventionally been used to create gettering sites in silicon substrates on which semiconductor devices are fabricated (1). The methods include intrinsic gettering, in which thermal treatments are used to create both a defect-free zone at the surface of the substrate wafers, where the devices are formed, and a deeper, defective bulk area where impurities are gettered. Other techniques include extrinsic gettering, by providing a highly doped polysilicon layer on the back surface of the wafer or by creating mechanical damage on the back surface. Alternatively, a lightly doped epitaxial layer formed on a heavily doped substrate will provide gettering by segregation at the epitaxy-substrate interface.In SOI wafers, however, these types of gettering technique are not efficient, because the buried oxide layer acts as a barrier to prevent the diffusion of most types of impurity out of the active silicon region into the bulk and back surface of the wafer where the gettering sites are normally formed. Therefore, the impurities remain in the SOI region and will potentially degrade devices fabricated using standard semiconductor device manufacturing methods. It is possible that the degree of gettering of impurities in the SOI layer may be influenced by such factors as the SOI material, the position of the bonding interface and the fabrication method. One technique to overcome this is to provide a highly doped implanted gettering layer in the top surface of the SOI wafer, close to the devices, while another technique is to provide trenches around devices, which can getter impurities through mechanically-induced or stress-induced defect generation in the silicon material. However, both these methods have the disadvantage that substantial ECS Transactions, 3 (4) 469-480 (2006) 10.1149/1.2355779, copyright The Electrochemical Society 469 ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 141.211.4.224 Downloaded on 2015-07-17 to...

Semiconductor Wafer Bonding is a key process step for many technologies such as engineered substrates (SOI and cavity SOI Wafers) MEMS (sensors, microfluidics), 3D integration (device stacking) and wafer thinning (temporary wafer bonding). Almost all publications in the field of wafer bonding are concerned with how bonding is working and can be performed at the actual wafer area. It is also well known that any disturbances on the wafer surface, such as particles, scratches, areas with increased surface roughness, or steps from the wafer processing act in most of the wafer bonding technologies as points of discontinuities with negative influences on the bonding behavior (generation of voids, non-hermeticity, reduced bonding strength). Due to the general geometry of the wafers and their defined sizes they have an edge. This wafer edge has special properties and also acts as an area of discontinuities. Even in well-established wafer bonding techniques, which allow close to perfect bonding of the wafer area, at the wafer edge there are smaller or wider unbonded areas. In particular, in industrial production processes, these unbonded areas are often the cause of process problems in the process steps after wafer bonding. For example, wet chemicals can be tapped in such unbonded areas and become released later into other tools, parts of the poorly bonded wafer edge can flake off, and in the grinding process wafers can break due to missing mechanical support at unbonded edge areas. The reasons for these unbonded areas can originate in different process areas such as the raw wafer manufacturing (here the wafer edge is initially defined), in the wafer processing before bonding (for every process step the wafer edge is a zone of discontinuities with special effects and inhomogeneities), in the bonding process (here the bonding needs to be formed until the very edge of the wafer) and in the process steps after the wafer bonding (bonded wafer edges can be easily damaged). In the proposed paper the influence of wafer edge effects on different wafer bonding technologies, such as direct, anodic and glass frit bonding, will be discussed, and improvements will be described. In this abstract, only one short example will be given: Semiconductor wafer bonding is used to process cavity SOI-Wafers to allow the advantageous production of absolute pressure sensors. Here, two kinds of wafers, which later become the pressure sensor membrane by grinding and polishing, have to be bonded to a carrier wafer containing etched cavities. For discrete pressure sensors, the use of bulk wafers is sufficient for the membrane, but due to the edge roll-off, a very slight transition from the actual wafer edge to the actual wafer area, some unbonded areas occur at the wafer edge, which disturb the subsequent processing (chemical trapping, flaking). For CMOS integrated pressure sensors, epi-wafers need to be used as membrane wafers. These epi wafers often have a so-called epi crown, a ridge at the wafer edge resulting from the growth of the epitaxial layer. This epi crown, over a wide area, prevents both wafers from coming into the required close contact to form the direct bond. This results in a poor bonding yield, and the wafers often cannot even be processed further on production tools. To allow bonding up to the wafer edge, special unsymmetrical edge geometries with reduced edge roll off, can be used for the bulk wafers [1]. To engineer the bonded wafer edge in advance, the wafer edge can be lowered in a defined way before the direct bonding by masking and silicon etching processes, to produce a very clean, well bonded wafer edge after grinding and polishing of the membrane wafer [2]. This preparation process removes the epi crown, thus allowing a very good bonding yield when bonding epi-wafers. It can be also used for bulk wafers to obtain a very defined wafer edge (see figure 1). It can be concluded that the wafer edge is a zone of discontinuities causing problems during wafer bonding. If the bonding problems at the edge are understood, they can be solved efficiently by suitable countermeasures. References: [1] R. Knechtel, A. Lenz: DE000010355728B4 Verbinden von Halbleiterscheiben gleichen Durchmessers zum Erhalt einer gebondeten Scheibenanordnung [2] R. Knechtel, U. Schwarz: DE102007025649B4 Verfahren zum Übertragen einer Epitaxie-Schicht von einer Spender- auf eine Systemscheibe der Mikrosystemtechnik Figure 1