The Role of Wafer Edge in Wafer Bonding Technologies

Abstract

Semiconductor Wafer Bonding is a key process step for many technologies such as engineered substrates (SOI and cavity SOI Wafers) MEMS (sensors, microfluidics), 3D integration (device stacking) and wafer thinning (temporary wafer bonding). Almost all publications in the field of wafer bonding are concerned with how bonding is working and can be performed at the actual wafer area. It is also well known that any disturbances on the wafer surface, such as particles, scratches, areas with increased surface roughness, or steps from the wafer processing act in most of the wafer bonding technologies as points of discontinuities with negative influences on the bonding behavior (generation of voids, non-hermeticity, reduced bonding strength). Due to the general geometry of the wafers and their defined sizes they have an edge. This wafer edge has special properties and also acts as an area of discontinuities. Even in well-established wafer bonding techniques, which allow close to perfect bonding of the wafer area, at the wafer edge there are smaller or wider unbonded areas. In particular, in industrial production processes, these unbonded areas are often the cause of process problems in the process steps after wafer bonding. For example, wet chemicals can be tapped in such unbonded areas and become released later into other tools, parts of the poorly bonded wafer edge can flake off, and in the grinding process wafers can break due to missing mechanical support at unbonded edge areas. The reasons for these unbonded areas can originate in different process areas such as the raw wafer manufacturing (here the wafer edge is initially defined), in the wafer processing before bonding (for every process step the wafer edge is a zone of discontinuities with special effects and inhomogeneities), in the bonding process (here the bonding needs to be formed until the very edge of the wafer) and in the process steps after the wafer bonding (bonded wafer edges can be easily damaged). In the proposed paper the influence of wafer edge effects on different wafer bonding technologies, such as direct, anodic and glass frit bonding, will be discussed, and improvements will be described. In this abstract, only one short example will be given: Semiconductor wafer bonding is used to process cavity SOI-Wafers to allow the advantageous production of absolute pressure sensors. Here, two kinds of wafers, which later become the pressure sensor membrane by grinding and polishing, have to be bonded to a carrier wafer containing etched cavities. For discrete pressure sensors, the use of bulk wafers is sufficient for the membrane, but due to the edge roll-off, a very slight transition from the actual wafer edge to the actual wafer area, some unbonded areas occur at the wafer edge, which disturb the subsequent processing (chemical trapping, flaking). For CMOS integrated pressure sensors, epi-wafers need to be used as membrane wafers. These epi wafers often have a so-called epi crown, a ridge at the wafer edge resulting from the growth of the epitaxial layer. This epi crown, over a wide area, prevents both wafers from coming into the required close contact to form the direct bond. This results in a poor bonding yield, and the wafers often cannot even be processed further on production tools. To allow bonding up to the wafer edge, special unsymmetrical edge geometries with reduced edge roll off, can be used for the bulk wafers [1]. To engineer the bonded wafer edge in advance, the wafer edge can be lowered in a defined way before the direct bonding by masking and silicon etching processes, to produce a very clean, well bonded wafer edge after grinding and polishing of the membrane wafer [2]. This preparation process removes the epi crown, thus allowing a very good bonding yield when bonding epi-wafers. It can be also used for bulk wafers to obtain a very defined wafer edge (see figure 1). It can be concluded that the wafer edge is a zone of discontinuities causing problems during wafer bonding. If the bonding problems at the edge are understood, they can be solved efficiently by suitable countermeasures. References: [1] R. Knechtel, A. Lenz: DE000010355728B4 Verbinden von Halbleiterscheiben gleichen Durchmessers zum Erhalt einer gebondeten Scheibenanordnung [2] R. Knechtel, U. Schwarz: DE102007025649B4 Verfahren zum Übertragen einer Epitaxie-Schicht von einer Spender- auf eine Systemscheibe der Mikrosystemtechnik Figure 1

Prediction of wafer handling-induced point defects in 300 mm silicon wafer manufacturing from edge geometric data

“…The silicon (Si) wafer properties such as global flatness (bow, warp, total thickness variation (TTV), and global backside ideal range (GBIR)), site flatness (site frontsurface-referenced least squares/range (SFQR), and nano-topography (NT)), near-edge geometries (edge site frontsurface-referenced least squares/range (ESFQR)),and edge roll-off (ERO) parameter, i.e. z-height double derivative (ZDD), are the key product parameters in the manufacturing of polished and epitaxial wafers [1,2], silicon-oninsulator (SOI) [3,4], and other layer conditions, including microelectromechanical systems (MEMS) [5,6] that employ wafer-to-wafer bonding and ultra-wafer thinning processes [7,8]. Process-induced defects (PIDs) are one of the three types of surface defects (crystal-originated pits, surface-adhered foreign particles, and PIDs) classified in Si wafer manufacturing [9,10].…”

Prediction of Wafer Handling-Induced Point Defects in 300 mm Silicon Wafer Manufacturing from Edge Geometric Data

“…The silicon (Si) wafer properties such as global flatness (bow, warp, total thickness variation (TTV), and global backside ideal range (GBIR)), site flatness (site front surface-referenced least squares/range (SFQR), and nano-topography (NT)), near-edge geometries (edge site front surfacereferenced least squares/range (ESFQR)),and edge roll-off (ERO) parameter, i.e. z-height double derivative (ZDD), are the key product parameters in the manufacturing of polished and epitaxial wafers [1,2], silicon-on-insulator (SOI) [3,4], and other layer conditions, including microelectromechanical systems (MEMS) [5,6] that employ wafer-to-wafer bonding [7,8] and ultrawafer thinning processes [9,10]. Process-induced defects (PIDs) are one of the three types of surface defects (crystal-originated pits, surface-adhered foreign particles, and PIDs) classified in Si wafer manufacturing [11,12].…”