Developing an accurate means of classifying defects, such as crystal-originated pits, surface-adhered foreign particles, and process-induced defects, using scanning surface inspection systems (SSIS) is of paramount importance because it provides the opportunity to determine the root causes of defects, which is valuable for yield enhancement. This report presents a novel defect classification approach developed by optimizing the linear-based channeling (LBC) and rule-based binning (RBB) algorithms that are applied to a commercially available SSIS (KLA-SP5), in combination with test sample selection including the signature defect patterns associated with the typical crystal growth process. The experimental results demonstrate that defect classification is possible with an accuracy and purity above 80% using the LBC algorithm and 90% using the RBB algorithm.

For the miniaturization of the structures of semiconductor device fabrication, high uniformity of side-flatness and edge roll-off of 300 mm wafers are required. In this study, the formation of light point defects (LPDs) on silicon (Si) wafer surface due to an edge gripper handling system was investigated. The relationships between the generation of LPDs with respect to flatness, edge profile, and edge roll-off of Si wafers were analyzed. It was found that the variation of tradition facet parameters and near-edge geometry metric, such as edge site front surface-referenced least squares/range (ESFQR), have no impact on the formation of surface LPDs. By contrast, the performance of Z-height double derivative (ZDD), allowed an accurate prediction of formation of surface LPDs. Additionally, for a 300mm silicon wafer, the surface LPDs occurred with frontside ZDD obtained at a radius of 149.2 mm, ranging above -954 nm/mm2 . The surface was LPDs free when ZDD was below -1235 nm/mm2. Surface LPD formation occurred randomly and was not predictable when ZDD ranged from -954 nm/mm2 to -1235 nm/mm2. The result indicates that the LPDs caused by wafer handling is proportional to the performance of ZDD at the edge roll-off area of silicon wafer, this is consistent with the requirement of edge roll-off considering wafer geometry.