Surface Defect Classification in Silicon Wafer Manufacturing Using the Linear-Based Channeling and Rule-Based Binning Algorithms

Hu, Hao; Ullakko, K.; Chao, Ming Ming; Lai, Xinmin

doi:10.4028/p-0612s4

Cited by 7 publications

(4 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In the contemporary technological landscape, the notable improvement in industrial technology has made it possible to precisely control the growth conditions as required. And the advanced analytical testing methods 17 have also provided an effective tool for evaluating the growth conditions according to the defect distribution in the resultant Si wafers. However, the rapid pace of development within the semiconductor industry has concurrently placed a heavy premium on the quality of large-sized Si wafers, thereby presenting a formidable challenge in accurately managing defect distribution, particularly along the radial direction.…”

Section: Introductionmentioning

confidence: 99%

Impact of Thermal Stress on Intrinsic Point Defect in Czochralski Crystal Growth: Developing a Quantitative Model for Defect Formation and Distribution

Hu,

He,

Pei

et al. 2024

Crystal Growth & Design

Self Cite

View full text Add to dashboard Cite

The distribution of intrinsic point defects, comprising vacancies and self-interstitials, plays a pivotal role in determining the quality and properties of silicon wafers, with profound implications for their applications in the semiconductor industry. Previous research posits that the dominant defect type in Czochralski (Cz) Si can be manipulated by adjusting the ratio of the pulling rate (V) to the axial thermal gradient (G). The critical value of V G establishes the equilibrium between vacancies and selfinterstitials. However, conventional theories often consider ( )to be a constant based on the assumption of thermal equilibrium.In this study, we present evidence that the formation and diffusion of the intrinsic point defects are influenced by thermal stress, rendering ( ) V G crit dependent on thermal stress distribution. Through a combination of first-principles calculations and finite element simulations, we establish a quantitative theoretical model that considers thermal stress. Based on this model, the impact of thermal stress on the defect distribution during Cz Si growth and the value of ( ) V G crit is elucidated. Our findings are validated through experimental growth of Cz Si and analytical testings. This work not only contributes to a deeper understanding of the microscopic mechanisms governing defect dynamics in Si but also advances Cz Si growth technology, ultimately enhancing the quality of the resultant Si wafers.

show abstract

Section: Introductionmentioning

confidence: 99%

Impact of Thermal Stress on Intrinsic Point Defect in Czochralski Crystal Growth: Developing a Quantitative Model for Defect Formation and Distribution

Hu,

He,

Pei

et al. 2024

Crystal Growth & Design

Self Cite

View full text Add to dashboard Cite

show abstract

“…z-height double derivative (ZDD), are the key product parameters in the manufacturing of polished and epitaxial wafers [1,2], silicon-oninsulator (SOI) [3,4], and other layer conditions, including microelectromechanical systems (MEMS) [5,6] that employ wafer-to-wafer bonding and ultra-wafer thinning processes [7,8]. Process-induced defects (PIDs) are one of the three types of surface defects (crystal-originated pits, surface-adhered foreign particles, and PIDs) classified in Si wafer manufacturing [9,10]. PIDs are captured as light point defects (LPDs) using commercially available scanning surface inspection systems (SSIS), such as Surf-scan SP5 (KLA, California, USA).…”

Section: Introductionmentioning

confidence: 99%

Prediction of wafer handling-induced point defects in 300 mm silicon wafer manufacturing from edge geometric data

Hu¹

2023

Preprint

View full text Add to dashboard Cite

<p>Abstract- For the miniaturization of the structures of semiconductor device fabrication, high uniformity of side-flatness and edge roll-off of 300 mm wafers are required. In this study, the formation of light point defects (LPDs) on silicon (Si) wafer surface due to an edge gripper handling system was investigated. The relationships between the generation of LPDs with respect to flatness, edge profile, and edge roll-off of Si wafers were analyzed. It was found that the variation of traditionfacet parameters and near-edge geometry metric, such as edge site frontsurface-referenced least squares/range (ESFQR), have no impact on the formation of surface LPDs. By contrast, the performance of Z-height double derivative (ZDD), allowed an accurate prediction of formation of surface LPDs. Additionly, for a 300mm silicon wafer, the surface LPDs occurred with frontside ZDD obtained at a radius of 149.2 mm, ranging above -954 nm/mm2 . The surface was LPDs free when ZDD was below -1235 nm/mm2 . Surface LPD formation occurred randomly and was not predictable when ZDD ranged from -954 nm/mm2 to -1235 nm/mm2 . The result indicates that the LPDs caused by wafer handling is proportional to the performance of ZDD at the edge roll-off area of silicon wafer, this is consistent with the requirement of edge roll-off considering wafer geometry.</p>

show abstract

“…z-height double derivative (ZDD), are the key product parameters in the manufacturing of polished and epitaxial wafers [1,2], silicon-on-insulator (SOI) [3,4], and other layer conditions, including microelectromechanical systems (MEMS) [5,6] that employ wafer-to-wafer bonding [7,8] and ultrawafer thinning processes [9,10]. Process-induced defects (PIDs) are one of the three types of surface defects (crystal-originated pits, surface-adhered foreign particles, and PIDs) classified in Si wafer manufacturing [11,12]. PIDs are captured as light point defects (LPDs) using commercially available scanning surface inspection systems (SSIS), such as Surf-scan SP5 (KLA, California, USA).…”

Section: Introductionmentioning

confidence: 99%

Prediction of Wafer Handling-Induced Point Defects in 300 mm Silicon Wafer Manufacturing from Edge Geometric Data

Lai²,

Chao³

et al. 2023

SSP

Self Cite

View full text Add to dashboard Cite

For the miniaturization of the structures of semiconductor device fabrication, high uniformity of side-flatness and edge roll-off of 300 mm wafers are required. In this study, the formation of light point defects (LPDs) on silicon (Si) wafer surface due to an edge gripper handling system was investigated. The relationships between the generation of LPDs with respect to flatness, edge profile, and edge roll-off of Si wafers were analyzed. It was found that the variation of tradition facet parameters and near-edge geometry metric, such as edge site front surface-referenced least squares/range (ESFQR), have no impact on the formation of surface LPDs. By contrast, the performance of Z-height double derivative (ZDD), allowed an accurate prediction of formation of surface LPDs. Additionally, for a 300mm silicon wafer, the surface LPDs occurred with frontside ZDD obtained at a radius of 149.2 mm, ranging above -954 nm/mm2 . The surface was LPDs free when ZDD was below -1235 nm/mm2. Surface LPD formation occurred randomly and was not predictable when ZDD ranged from -954 nm/mm2 to -1235 nm/mm2. The result indicates that the LPDs caused by wafer handling is proportional to the performance of ZDD at the edge roll-off area of silicon wafer, this is consistent with the requirement of edge roll-off considering wafer geometry.

show abstract

Surface Defect Classification in Silicon Wafer Manufacturing Using the Linear-Based Channeling and Rule-Based Binning Algorithms

Cited by 7 publications

References 25 publications

Impact of Thermal Stress on Intrinsic Point Defect in Czochralski Crystal Growth: Developing a Quantitative Model for Defect Formation and Distribution

Impact of Thermal Stress on Intrinsic Point Defect in Czochralski Crystal Growth: Developing a Quantitative Model for Defect Formation and Distribution

Prediction of wafer handling-induced point defects in 300 mm silicon wafer manufacturing from edge geometric data

Prediction of Wafer Handling-Induced Point Defects in 300 mm Silicon Wafer Manufacturing from Edge Geometric Data

Contact Info

Product

Resources

About