Effect of metal layout design on passivation crack occurrence using both experimental and simulation techniques

Abstract

Thermo -mechanical reliability is one of the concerns for semiconductor developments due to miniaturization, introduction of new materials, and higher application temperatures. FE modeling techniques are developed to predict the effect of IC interconnect metal designs on the thermo -mechanically -induced cracking of passivation layers. Experimental techniques on specially designed IC packages are developed to verify the predicted passivation cracks. With the verified 2D and 3D models, various simulations are performed and it is established that delamination of IC/compound interface is a key trigger for passivation cracking. When delamination is present, crack occurrence is found to depend on the metal layout and location on the IC. Optimizing the metal layout design can even prevent passivation cracks. By combining efficient & accurate simulations with a limited number of experiments, passivation crack can be quantitatively predicted prior to physical prototyping.

Impact of IC wafer fab and assembly fab processes on package stress induced product reliability issues - an insight into the package stress relief design rules by simulation

“…It is therefore important to verify the simulation results with experiments. Parts of the verifications have been covered in earlier publications [4,5]. In this section more details are to be shared with the readers.…”

“…4 and 5. A detailed description of the simulation methodology can be found in the references [2][3][4][5]. A typical IC layer stack of 6 metals is taken in the simulations on a Si substrate of (100) orientation as is mostly used in the industry.…”

“…A lot of work has been done to develop reliable models for simulations of IC package stress related issues [2][3][4][5]. In this work the layout of the chip and the most relevant process and material parameters of IC wafer fab and assembly fab are taken into account in the simulations combined with experimental verification to study the impact of those parameters on the package stress induced damages.…”

“…Thermo-mechanical simulation is a powerful tool in dealing with thermo-mechanical related problems [1][2][3][4][5][6][7]. A lot of work has been done to develop reliable models for simulations of IC package stress related issues [2][3][4][5].…”

Facing the challenge of designing for Cu/low-k reliability

“…FE techniques are widely used to predict the deformations and stresses and their evolution during IC processes, packaging manufacturing processes, and/or product testing [4,5,8,[17][18][19][20][21][22][23][24][25][26]. Modelling techniques such as contact elements, global-local, sub-structuring, element birth and death, fracture mechanics and material models such as visco-elasticity, plasticity and creep are rapidly developed to predict the stress and strain state in the electronic Fig.…”