Effect of Metallic Contamination on Interface Properties and Oxide Reliability

Abstract

New and emerging process technologies such as Damascene interconnect, metal gate and metal silicide processes are creating metal contamination control challenges for current and future generations of integrated circuits. In this work, we studied the contamination of oxidized silicon wafers by several metals of industrial importance including copper, cobalt, sodium, iron and nickel. Contamination was applied by spin-coating in a range from 20ppb to 500 ppb. Such levels are representative of exposure challenges induced during chemical processes such as CMP (chemical mechanical planarization) cleans. Solvated contamination ions were driven into the oxide layer by corona temperature stress (CTS). The concentrations of metallic species incorporated within the oxide by CTS were quantified using VPD-ICPMS (vapor phase decomposition) and SIMS (secondary ion mass spectrometry) surface analysis techniques. Noncontact COCOS (Corona Oxide Characterization of Semiconductor) methods were employed to measure the electrical properties and reliability of nascent and contaminated oxide/silicon structures. We show that in the absence of significant signals from the surface analysis techniques the COCOS methods show signatures of the metallic contamination in the measurement results.

A Highly Sensitive Determination of Bulk Cu and Ni in Heavily Boron-doped Silicon Wafers

“…Nano-scale device processes having a low thermal budget are more sensitive to metal contamination than previous processes [1][2][3][4] and are particularly susceptible to Cu and Ni, which are considered to be detrimental to the performance of these devices. [5][6][7][8][9][10][11][12][13][14] However, progress on the metrology for analysis of bulk Cu and Ni has been relatively slow. Due to lack of commercially available bulk metal standards and poor recovery yield in heavily boron-doped silicon wafers, analytical accuracy and precision cannot, so far, be guaranteed.…”

Test Methods for Measuring Bulk Copper and Nickel in Heavily Doped p-Type Silicon Wafers

“…Nanoscale device processes with a low thermal budget can strongly be affected by bulk metal contamination, [1][2][3][4] particularly Cu and Ni, which could be detrimental to the device performance. [5][6][7][8][9][10][11][12][13][14][15][16] However, both detection and removal of bulk Cu and Ni impurities in the heavily doped p-type silicon wafers are complicated due to the possibility of interaction of Cu with boron and formation of Ni silicides. [17][18][19][20][21][22][23][24] The detection of bulk Cu and Ni impurities below 1 ϫ 10 13 atoms/cm 3 in the heavily doped p-type silicon wafers is challenging, particularly in high-volume manufacturing ͑HVM͒.…”