A sequence of noncontact corona-Kelvin metrology is introduced that enables the determination and monitoring of interface properties in dielectric/wide band gap semiconductor structures. The technique involves the incremental application of precise and measured quantities of corona charge, QC, onto the dielectric surface followed by determination of the contact potential difference, VCPD, as the material structure response. The V-Q characteristics obtained are used to extract the surface barrier, VSB, response related to the applied corona charge. The described approach differs from the common noncontact method applied in the case of dielectric/silicon structures where for each quanta of applied charge the value of surface barrier voltage, VSB, is obtained. Materials with wide band gaps and high concentrations of deep levels, as suggested for silicon carbide, do not permit quick determination of VSB by modulation of the band bending in the semiconductor with light. Light exposure in the case of SiC results in a long recovery time required to approach the nominal value of the preillumination VCPD value. The metrology approach presented determines an intersection of the VCPD-QC characteristic obtained in the dark with the Vox-QC characteristic representing the dielectric response. The specific VSB-QC dependence surrounding the reference VFB value is obtained from this approach and enables the noncontact determination of the dielectric interface trap density and its spectrum. Application of the modified metrology method to thermal oxide on n-type 4H-SiC demonstrates the modification of the Dit distribution by Fowler–Nordheim stress. In addition, an ability to quantify and separate trapped charge components is shown.

Non-basal surfaces of 6H-SiC, which are thought to exhibit polar behaviour, were thermally oxidized in steam. The resulting oxide thickness was determined by two methods: a non-contact measurement of the oxide capacitance and a physical measurement of the step height from an etched pattern. The surface was found to oxidize faster than its counterpart, i.e. the surface. When these results were compared with results of the oxidation of the basal {0001} and surfaces, the effective permittivity of the oxide was found to be closer to the ideal value of 3.9 for SiO2 grown on the and surfaces. This important result for these novel crystalline surfaces could be beneficial in the fabrication of MOSFET devices on SiC.

We present a very fast, non-contact and preparation free method of determining doping concentration and doping depths profiles in silicon carbide epitaxial layers. The method is an extension of the recently patented Q 2 -V technique. It uses a corona discharge in air for charging the epi-surface with precisely controlled doses of electrical charge, ∆Q C . Corona charging is followed by non-contact measurement of the surface potential, V, using a vibrating probe. A sequence of charging and measuring steps produces the Q 2 -V plot that for uniform doping satisfies a linear relation. For nonuniform doping a depth profile is obtained from a derivative, dQ 2 /dV, similar to the derivative capacitance method.

New and emerging process technologies such as Damascene interconnect, metal gate and metal silicide processes are creating metal contamination control challenges for current and future generations of integrated circuits. In this work, we studied the contamination of oxidized silicon wafers by several metals of industrial importance including copper, cobalt, sodium, iron and nickel. Contamination was applied by spin-coating in a range from 20ppb to 500 ppb. Such levels are representative of exposure challenges induced during chemical processes such as CMP (chemical mechanical planarization) cleans. Solvated contamination ions were driven into the oxide layer by corona temperature stress (CTS). The concentrations of metallic species incorporated within the oxide by CTS were quantified using VPD-ICPMS (vapor phase decomposition) and SIMS (secondary ion mass spectrometry) surface analysis techniques. Noncontact COCOS (Corona Oxide Characterization of Semiconductor) methods were employed to measure the electrical properties and reliability of nascent and contaminated oxide/silicon structures. We show that in the absence of significant signals from the surface analysis techniques the COCOS methods show signatures of the metallic contamination in the measurement results.

In this work SiO 2 on silicon was contaminated with metal-containing solutions after it was grown. Significant deleterious electrical effects are shown to develop following oxide surface contamination with part per billion, ppB, levels of metals from solution. The objective was to address the risk that unintentional contamination, such as may occur during routine manufacturing processes, posed to oxide electrical performance. Accordingly, high temperature or ion implantation-based contamination process environments, typical of previous studies, were not used in this work. Two low-energy methods were developed to introduce the contamination to the oxide and they are referred to as unintentional contamination mimic and plasma mimic processes, respectively. Equilibrium current density vs oxide stress field, J-E OX , capacitor measurements were used to assess the degradation in oxide quality caused by exposure to either cobalt, copper, nickel, or iron containing solutions. Cobalt was observed to act in a fashion different from other metals at low ppB contamination levels for capacitor structures, suggesting a different behavior of this metal when applied to oxide relative to the other metals considered. Further, a strong correlation is demonstrated between capacitor measurement results and noncontact oxide stress-induced-leakage-current, measurements that do not require capacitor fabrication.