2009
DOI: 10.1109/irps.2009.5173363
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Effect of multiple via layout on electromigration performance and current density distribution in copper interconnect

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Cited by 11 publications
(8 citation statements)
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“…However, the reduction in the number of contacts results in an increase in the current density at each contact, and a higher temperature rise and temperature gradient [22] are resulted, which in turn increase the value of AFD_SM and total AFD. The simulation result reflects a reduction in the void nucleation time with fewer contacts, which agrees with the reported experimental observations in [23]. As the void nucleation time occupy a large portion of the EM lifetime [24], a smaller void formation time reflects a smaller EM lifetime of the circuit.…”
Section: Case Of the Class Ab Amplifiersupporting
confidence: 87%
“…However, the reduction in the number of contacts results in an increase in the current density at each contact, and a higher temperature rise and temperature gradient [22] are resulted, which in turn increase the value of AFD_SM and total AFD. The simulation result reflects a reduction in the void nucleation time with fewer contacts, which agrees with the reported experimental observations in [23]. As the void nucleation time occupy a large portion of the EM lifetime [24], a smaller void formation time reflects a smaller EM lifetime of the circuit.…”
Section: Case Of the Class Ab Amplifiersupporting
confidence: 87%
“…The rise in temperature of the models at the end of one load cycle is less than 0. fewer contacts. This result is expected and it agrees with the reported experimental observations in [117,118]. The observation also agrees with the design rule for preventing EM.…”
Section: Effects Of the Interconnect Structures On The Circuit Em Relsupporting
confidence: 92%
“…above 8.05x10 9 atoms/µm 3 •s for the circuit structure and 1.27x10 10 atoms/µm 3 •s for the line-via test structure). This result is consistent with the experimental results in literature[117,118].However, a test temperature of 300 o C is too high for the circuit under actual operation because most of the circuit components are not able to function well at above 125 o C and the chip packaging will change its properties significantly above its glass transition temperature which is 260 o C for the commonly used packaging materials in IC packaging[85]. The simulation is performed again at a circuit operation temperature of 90 o C and the results are shown inFig.…”
supporting
confidence: 94%
“…EM has been widely studied in various ways from physical test structures, such as interconnect length [9,10], width [11,12], multi-via structure [12,13] and so on. The reservoir region is referred as the extended length and/or areas and/or volumes of metal from the vias [14][15][16][17][18][19].…”
Section: Motivationmentioning
confidence: 99%