Effect of Post-metallization Annealing for Alternative Gate Stack Devices

Abstract

To meet the gate leakage specifications in the International Technology Roadmap for Semiconductors (ITRS), an intensive search is being conducted for alternative gate stack materials. Most of the studies have focused on basic material properties, but very little effort has been directed towards quantifying and understanding the effect of post metallization annealing (PMA) on the electrical properties of the dielectric. In this work, devices were fabricated with a "gate last" process. The gate dielectrics studied included: HfO 2 deposited by PVD or MOCVD, as well as Y 2 O 3 and La 2 O 3 deposited by RPECVD and MBE, respectively. Poly-Si gate electrodes were prepared by 600°C LPCVD followed by ion implantation and dopant activation using 900°C 60sec RTA. Device characteristics were measured before and after 20 min 400-450°C forming gas (FG, 10% H 2 Here the mobility parameters, including EOT, were extracted from device I-V data based on the assumptions that: a) EOT was not affected by PMA and b) the post-PMA scattering parameters were the same as good SiO 2 (3e10/cm 2 ). Peak mobility of 63% and 57% higher were observed for La 2 O 3 and Y 2 O 3 , respectively. Dramatic reductions in interface scattering charges were observed: from 19 and 11 e10/cm 2 for Y 2 O 3 and La 2 O 3 respectively, to 3e10/cm 2 . The roughness scattering parameters did not change much. It seems that the FG post metallization annealing reduces interface charge also for group III materials. The gate leakage was not affected by PMA for either material.

Chemical surface passivation of HfO2films in a ZnO nanowire transistor

“…In addition, the amount of surface adsorbed oxygen species sharply declines from 53.5 to 39.4% as the annealing atmosphere alters from N 2 to H 2 ambient. This suggests that oxygen species could hardly attach to the surface of the HfO 2 films due to the hydrogen passivation [12][13][14].…”

“…However, the performance of these devices is severely constrainted due to the low dielectric constant of SiO 2 gate dielectric layers. In contrast, HfO 2 has steadily emerged as an important candidate to work as a gate insulator due to its high dielectric constant and relatively low leakage current [6][7][8][9][10][11][12][13][14]. As a result, integrating ZnO nanowire FETs with HfO 2 gate insulators is expected to deliver substantially enhanced device performance such as transconductance (g m ), current on/off ratio (I on /I off ), and carrier mobility (µ e ).…”

Erbium Silicide Growth in the Presence of Residual Oxygen

“…RE oxides [1][2][3][4] and silicates 5 find application as gate dielectrics because of their high relative permittivity. RE oxides [1][2][3][4] and silicates 5 find application as gate dielectrics because of their high relative permittivity.…”

“…In the recent years, the continuous trend to device miniaturization continuously requires the introduction of additional elements from Mendeleev's table in complementary metal-oxide-semiconductor (CMOS) technology, for instance, rare-earth (RE) metals. RE oxides [1][2][3][4] and silicates 5 find application as gate dielectrics because of their high relative permittivity. On the other hand, RE silicides are materials of interest for the formation of ohmic or low Schottky barrier contacts over lowly doped n-type Si substrates.…”

Effects of sputtering pressure and post-metallization annealing on the physical properties of rf-sputtered Y2O3 films

“…The change of pressure inside the discharge chamber can alter the probability of mutual collision between discharge ions and sputtered particles, which would greatly affect the mean free path of the sputtered particles and eventually the film quality. Besides in situ parameters, ex situ treatments also influence the quality of sputtered films, among which post-metallization annealing (PMA) is an effective method to polish the properties of both materials and devices [12,13]. More specifically, the low-temperature post-metallization annealing process has been regarded as a useful procedure in metal-oxide-semiconductor (MOS) technology to reduce the interface trap density by passivating and repairing oxide-related trap charge [15].…”