Effect of short-circuit stress on the degradation of the SiO2 dielectric in SiC power MOSFETs

Reigosa, Paula Diaz; Iannuzzo, Francesco; Ceccarelli, Lorenzo

doi:10.1016/j.microrel.2018.07.144

Cited by 43 publications

(19 citation statements)

References 19 publications

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“…For the third region (3), the device is placed under a small gate polarization (strong depolarization in Vgs), which generates an increase in Rds(on) and consequently losses in higher conduction. On the other hand, with a Vgs too close to Vgsth makes the device more sensitive to electron trapping effect at SiC/SiO2 interface and Vgsth drift [16][17]. Also, due to the variability of local Vgsth from one local MOSFET cell to another, a too low Vgs can lead to a high current density inhomogeneity of the chip surface in the channel regions.…”

Section: Failure Mode and Gate Voltage Depolarizationmentioning

confidence: 99%

Towards a safe failure mode under short-circuit operation of power SiC MOSFET using optimal gate source voltage depolarization

Jouha

Richardeau

Azzopardi

2021

Microelectronics Reliability

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This paper focuses on the enhancement of the robustness level of SiC MOSFET during short-circuit conditions. In this study, two approaches allowing to ensure safe "Fail-To-Open" (FTO) mode in planar power SiC MOSFET devices under shortcircuit operation are presented. These approaches are based on direct depolarization of the gate source voltage and its estimation from the calculation of the critical dissipated power (W/mm²) between FTO and classical unsafe thermal runaway. They allow to determine the maximum value of the gate source voltage to preserve a FTO mode under a drain source voltage close to the nominal value i.e VBRmin / 2. The boundary of the power density between FTO and "Fail-To-Short" (FTS) is introduced. A complete experimentation of the two failure modes in competition that may appear during short-circuit (SC) test of 1.2 kV SiC MOSFETs is presented. Finally, the penalty of the gate source voltage depolarization on the on-state resistance (Rds(on)) is investigated in order to evaluate the techniques efficiency.

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Section: Failure Mode and Gate Voltage Depolarizationmentioning

confidence: 99%

Towards a safe failure mode under short-circuit operation of power SiC MOSFET using optimal gate source voltage depolarization

Jouha

Richardeau

Azzopardi

2021

Microelectronics Reliability

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“…These different post cracks were a clear marker of a permeant physical degradation of the device. Different studies show the presence of the gate damage failure mode [25,26], and the successive degradations [27]. However, some authors have shown that it is also possible to partially restore the gate-integrity by a dedicated original gate-bias procedure, in off-line operation, provided that the gate is not totally cracked [28].…”

Section: Sequencementioning

confidence: 99%

VDS and VGS Depolarization Effect on SiC MOSFET Short-Circuit Withstand Capability Considering Partial Safe Failure-Mode

et al. 2021

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This paper presents a detailed analysis of 1200 V Silicon Carbide (SiC) power MOSFET exhibiting different short-circuit failure mechanisms and improvement in reliability by VDS and VGS depolarization. The device robustness has undergone an incremental pulse under different density decreasing; either drain-source voltage or gate-driver voltage. Unlike silicon device, the SiC MOSFET failure mechanism firstly displays specific gradual gate-cracks mechanism and progressive gate-damage accumulations greater than 4 µs/9 J·cm−2. Secondly, a classical drain-source thermal runaway appears, as for silicon devices, in a time greater than 9 µs. Correlations with short-circuit energy measurements and temperature simulations are investigated. It is shown that the first mechanism is an incremental soft gate-failure-mode which can be easily used to detect and protect the device by a direct feedback on the gate-driver. Furthermore, it is highlighted that this new mechanism can be sufficiently consolidated to avoid the second drain-source mechanism which is a hard-failure-mode. For this purpose, it is proposed to sufficiently depolarize the on-state gate-drive voltage to reduce the chip heating-rate and thus to decouple the failure modes. The device is much more robust with a short-circuit withstand time higher than 10 µs, as in silicon, no risk of thermal runaway and with an acceptable penalty on RDS-ON.

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“…1D electro-thermal-metallurgical (Al) simulation highlighting different stress levels. [11,12,13] failures [11]. Afterwards the device enters an ageing region, where the gate starts to weaken until the devices reaches Al solidus to liquidus temperature range, 933K.…”

Section: The Benefits Of a Sub-microsecond Detectionmentioning

confidence: 99%

Robustness study of a fast protection method based on the gate-charge dedicated for SiC MOSFETs power device

Barazi

Richardeau

Rouger

et al. 2021

Microelectronics Reliability

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This paper focuses on the extensive robustness validation of a gate charge detection method designed for SiC MOSFETs under short-circuit operation, and, in terms of failure-modes. The benefits of having a fast (submicrosecond -150ns) detection method is illustrated by a 1D thermo-metallurgical simulation. This method is integrated owing to an optimized SMD/PCB technology (Surface-Mount Device/ Printed Circuit Board).

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Effect of short-circuit stress on the degradation of the SiO2 dielectric in SiC power MOSFETs

Cited by 43 publications

References 19 publications

Towards a safe failure mode under short-circuit operation of power SiC MOSFET using optimal gate source voltage depolarization

Towards a safe failure mode under short-circuit operation of power SiC MOSFET using optimal gate source voltage depolarization

VDS and VGS Depolarization Effect on SiC MOSFET Short-Circuit Withstand Capability Considering Partial Safe Failure-Mode

Robustness study of a fast protection method based on the gate-charge dedicated for SiC MOSFETs power device

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