Towards a safe failure mode under short-circuit operation of power SiC MOSFET using optimal gate source voltage depolarization

Abstract

This paper focuses on the enhancement of the robustness level of SiC MOSFET during short-circuit conditions. In this study, two approaches allowing to ensure safe "Fail-To-Open" (FTO) mode in planar power SiC MOSFET devices under shortcircuit operation are presented. These approaches are based on direct depolarization of the gate source voltage and its estimation from the calculation of the critical dissipated power (W/mm²) between FTO and classical unsafe thermal runaway. They allow to determine the maximum value of the gate source voltage to preserve a FTO mode under a drain source voltage close to the nominal value i.e VBRmin / 2. The boundary of the power density between FTO and "Fail-To-Short" (FTS) is introduced. A complete experimentation of the two failure modes in competition that may appear during short-circuit (SC) test of 1.2 kV SiC MOSFETs is presented. Finally, the penalty of the gate source voltage depolarization on the on-state resistance (Rds(on)) is investigated in order to evaluate the techniques efficiency.

Gate-damage safe failure-mode deep analysis under short-circuit operation of 1.2kV and 1.7kV power SiC MOSFET using dedicated gate-source / drain-source voltage depolarization and damage-mode optical imaging

“…The short-circuit test methodology is performed with a three values of bus voltage (VDC) (500, 550 and 600V) and 10V < VGS < 13V to identify the maximum power density yielding a FTO mode [10] at TCASE = 25°C. Table 1 summarizes the results of short-circuit.…”

Measurements and Review of Failure Mechanisms and Reliability Constraints of 4H-SiC Power MOSFETs Under Short Circuit Events

“…Different from the failure mode caused by the rapid temperature rise, gate failure is more likely to happen under lower temperature and longer time duration (t sc ) occasions, which means the device is heated up at a lower speed, and the final temperature is not high enough to induce the massive generation of electron-hole pairs to cause thermal runaway [26], [28], [32].…”

SiC power MOSFET overload detection, short-circuit protection and gate-oxide integrity monitoring using a switched resistors dual-channel gate-driver

“…In addition to improvements in chip architecture design, another approach consists in functionalising the gate-driver to efficient shortcircuit / over-current handling and dedicated gateoxide health monitoring -conditioning strategies. Among the previous work of the authors on discrete 1.2kV and 1.7kV SiC power MOSFETs, it was shown in [3] [4] that the reduction of the short-circuit power density to 4kW/mm² made it possible to exceed the threshold of 10µs short-circuit withstand time capability (TSCW) and to bring the chip to a safe gatesource short and drain-source open failure mode (Failto-Open FTO mode). Other authors have confirmed this property [5].…”

“…Fig. 2 gives out the global setup used, based on a previously developed 600V-200J short-circuit 3-lead TO-247 device test bench [3], including the new dualchannel gate-driver for the low-side DUT. During the characterisation process, the high-side is equipped with a standard gate-driver.…”