Effect of Sn grain orientation and strain distribution in 20-μm-diameter microbumps on crack formation under thermal cycling tests

Chu, Yi Cheng; Chen, Chih; Kao, Nicholas; Jiang, Don Son

doi:10.1007/s13391-017-7041-5

Cited by 13 publications

(9 citation statements)

References 15 publications

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“…Normally, cracks initiate at the edge and propagate along grain boundaries or an interface [ 11 , 12 , 13 ]. Interestingly, we found that the cracks formed along the grain boundaries at the bonding interface center.…”

Section: Resultsmentioning

confidence: 99%

“…In a 3D IC device, solder microbumps have been widely used as interconnects between functional chips and an interposer [ 7 ]. Those solders severely suffer from electromigration [ 8 , 9 , 10 ] and thermal fatigue [ 11 , 12 , 13 ] during operations. In addition, the high resistance and downscaling of solder joints should be critically considered.…”

Section: Introductionmentioning

confidence: 99%

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Failure Mechanisms of Cu–Cu Bumps under Thermal Cycling

Shie

Hsu

et al. 2021

Materials

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The failure mechanisms of Cu–Cu bumps under thermal cycling test (TCT) were investigated. The resistance change of Cu–Cu bumps in chip corners was less than 20% after 1000 thermal cycles. Many cracks were found at the center of the bonding interface, assumed to be a result of weak grain boundaries. Finite element analysis (FEA) was performed to simulate the stress distribution under thermal cycling. The results show that the maximum stress was located close to the Cu redistribution lines (RDLs). With the TiW adhesion layer between the Cu–Cu bumps and RDLs, the bonding strength was strong enough to sustain the thermal stress. Additionally, the middle of the Cu–Cu bumps was subjected to tension. Some triple junctions with zig-zag grain boundaries after TCT were observed. From the pre-existing tiny voids at the bonding interface, cracks might initiate and propagate along the weak bonding interface. In order to avoid such failures, a postannealing bonding process was adopted to completely eliminate the bonding interface of Cu–Cu bumps. This study delivers a deep understanding of the thermal cycling reliability of Cu–Cu hybrid joints.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Failure Mechanisms of Cu–Cu Bumps under Thermal Cycling

Shie

Hsu

et al. 2021

Materials

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“…Segregation of the impure species or their derivatives in the grain boundaries might also annihilate the vacancy sinking sites which accelerated the accumulation of vacancies to form voids [14][15][16]. Severe void propagation gave rise to the formation of continuous crevices or cracks which was a kind of volumetric defects in crystal caused by void nucleation during annealing [17,18].…”

Section: Resultsmentioning

confidence: 99%

Effects of Impurity on Void Formation at Interface between Sn-3.0Ag-0.5Cu and Cu Electroplated Film

Chiang

Shen

Chen

2021

Preprint

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Void formation is a critical reliability concern for solder joints in electronic packaging. The control of microstructures and impurity quantities in Cu electroplated films significantly affects the void formation at the joint interface, but the studies for their comparison are seldom. In this study, three Cu films (termed as A, B, and C) are fabricated using an electroplating process. The Cu A film has a facted grain texture embedded with twins while Cu B and C have a similar columnar texture. After thermal aging at 200°C for 1000 h, the SAC 305 (Sn-3.0Ag-0.5Cu) solder joints with Cu A and B exhibit a robust interfacial structure without voids. However, microstructural collapse is observed in the solder joint of SAC 305/Cu C, where many crevives parallel to the interface are formed. Based on the microanalysis, the concentration of impurity is higher in the Cu C film than those in Cu A and B. Moreover, discrete voids rather than continuous crevices are presented in the SAC305/Cu C system when the impurity concentration in Cu C is reduced. The findings demonstrate that the impurity control in the Cu electroplated film is critical for the control of void/crevice formation in the electronic solder joints.

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“…However, there is little research on the damage of the neighboring un-powered micro-bumps prompted by thermal crosstalk. Y.-C. Chu et al [87] studied the thermo-mechanical properties of SnAg micro-bumps, finding that serious crack formation was observed in micro-bumps, and many cracks were propagated across the entire micro-bump along two main paths: Sn grain boundaries with high misorientation angles and SnAg solder/Ni 3 Sn 4 IMC interfaces. Further, as the average grain size was as small as 7.4 µm, and the diameter of micro-bumps was only 20 µm, many cracks were likely to propagate across the entire micro-bump, significantly weakening its mechanical and electrical properties.…”

Section: Micro-bump Electromigration and Heat Transfermentioning

confidence: 99%

“…The thermo-mechanical properties of SnAg micro-bumps Significantly weaken its mechanical and electrical properties. [87]…”

Section: Designed a Test Interposer For Popmentioning

confidence: 99%

TSV Technology and High-Energy Heavy Ions Radiation Impact Review

Tian

Liu

2018

Electronics

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Three-dimensional integrated circuits (3D IC) based on TSV (Through Silicon Via) technology is the latest packaging technology with the smallest size and quality. As a result, it can effectively reduce parasitic effects, improve work efficiency, reduce the power consumption of the chip, and so on. TSV-based silicon interposers have been applied in the ground environment. In order to meet the miniaturization, high performance and low-cost requirements of aerospace equipment, the adapter substrate is a better choice. However, the transfer substrate, as an important part of 3D integrated circuits, may accumulate charge due to heavy ion irradiation and further reduce the performance of the entire chip package in harsh space radiation environment or cause it to fail completely. Little research has been carried out until now. This article summarizes the research methods and conclusions of the research on silicon interposers and TSV technology in recent years, as well as the influence of high-energy heavy ions on semiconductor devices. Based on this, a series of research methods to study the effect of high-energy heavy ions on TSV and silicon adapter plates is proposed.Electronics 2018, 7, 112 2 of 29 wafer was invented by M.G Smith et al. [2], which opposite surfaces were connected ohmically to the degenerately doped portions to be electrically connected along the thru-connection. With further research and exploration, 2.5D/3D integration technology with TSV realized integrated circuits with advantages of high interconnection density, high performance, low power consumption, and low cost [3,4]. In addition, the core is widely considered to be the leading technology in the field of high density packaging in the future and is an effective way to break through Moore's Law [5][6][7]. Figure 1. Silicon interposer through electrical copper coating technology production: (a) The construction of through-silicon via on the wafer; (b) The dry film etchant is stuck on the wafer, then exposed and etched; (c) Hole plating and pad fabrication by electroplating methods; (d) The photoresist removing. Adapted with permission from [27], Copyright Elsevier, 2016.

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Effect of Sn grain orientation and strain distribution in 20-μm-diameter microbumps on crack formation under thermal cycling tests

Cited by 13 publications

References 15 publications

Failure Mechanisms of Cu–Cu Bumps under Thermal Cycling

Failure Mechanisms of Cu–Cu Bumps under Thermal Cycling

Effects of Impurity on Void Formation at Interface between Sn-3.0Ag-0.5Cu and Cu Electroplated Film

TSV Technology and High-Energy Heavy Ions Radiation Impact Review

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