Effect of substrate bias on the performance and reliability of the split-gate source-side injected flash memory

Huang, Kuo‐Ching; Fang, Yanping; Yaung, Dun–Nian; Chen, Chii-Wen; Sung, Hung-Cheng; Kuo, D.S.; Wang, C.S.; Liang, Mong–Song

doi:10.1109/55.778161

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Cited by 5 publications

(1 citation statement)

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“…In this paper, the erase voltage impact on the 0.18 m triple self-aligned split-gate flash endurance is investigated. Compared with previous studies OE16; 17 , both the tunnel oxide charge trapping and the select gate (SG) oxide charge trapping are taken into consideration. It is found that an optimized erase voltage exists for a certain tunnel oxide thickness.…”

Section: Introductionmentioning

confidence: 99%

Erase voltage impact on 0.18 μm triple self-aligned split-gate flash memory endurance

Dong

Kong

et al. 2010

J. Semicond.

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The erase voltage impact on the 0.18 m triple self-aligned split-gate flash endurance is studied. An optimized erase voltage is necessary in order to achieve the best endurance. A lower erase voltage can cause more cell current degradation by increasing its sensitivity to the floating gate voltage drop, which is induced by tunnel oxide charge trapping during program/erase cycling. A higher erase voltage also aggravates the endurance degradation by introducing select gate oxide charge trapping. A progressive erase voltage method is proposed and demonstrated to better balance the two degradation mechanisms and thus further improve endurance performance.

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Section: Introductionmentioning

confidence: 99%

Erase voltage impact on 0.18 μm triple self-aligned split-gate flash memory endurance

Dong

Kong

et al. 2010

J. Semicond.

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Device scaling considerations for sub-90-nm 2-bit/cell split-gate flash memory cell

Liu

et al. 2019

Solid-State Electronics

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Fabrication and optimization of aggressively scaled Dual-Bit/Cell Split-Gate Floating-Gate flash memory cell in 55-nm node technology

Chen

Xiong

et al. 2022

Solid-State Electronics

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Effect of substrate bias on the performance and reliability of the split-gate source-side injected flash memory

Cited by 5 publications

References 7 publications

Erase voltage impact on 0.18 μm triple self-aligned split-gate flash memory endurance

Erase voltage impact on 0.18 μm triple self-aligned split-gate flash memory endurance

Device scaling considerations for sub-90-nm 2-bit/cell split-gate flash memory cell

Fabrication and optimization of aggressively scaled Dual-Bit/Cell Split-Gate Floating-Gate flash memory cell in 55-nm node technology

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