Effect of Surface Treatments on the Electrical Properties of Fluorinated Silicon Oxides

Abstract

In this study, different surface treatments of HF-based etching solutions are investigated for the predeposition of liquid-phase deposited fluorinated silicon oxides (LPD-SiOF). The effects of each etching solution on the interface trap density and breakdown field are examined with Al/LPD-SiOF/Si structure. From the experimental results, there appears significant growth delay time for different surface treatments during the initial oxide deposition, which is defined as the surface modification time to reach an OHrich surface promoting the growth of LPD-SiOF film. However, the subsequent deposition rate remains unchanged for all etching processes, indicating a surface-independent deposition process. It is found that a two-step treatment in dilute HF/H 2 O with 1:200 v/v ratio reveals an average breakdown field of 9.7 MV/cm and an extremely low average interface trap density (ϳ10 10 eV Ϫ1 cm Ϫ2), which are comparable to that of thermal oxides. Moreover, the rapid thermal annealing process is suggested to clearly improve the oxide quality for this two-step etching process, where early breakdown is eliminated (18% raising for E BD) and interface properties are substantially improved (33% reduction for D H). The improvements for device performances are believed to be due to the oxide-free Si surface passivated with hydrogen and reduced surface microroughness (Ra ϭ 0.1 nm). It is evident from our experiments that this new two-step surface treatment is an effective method for interface improvement with oxide deposited by LPD or chemical vapor deposition.

Electrical properties and modeling of ultrathin impurity-doped silicon dioxides

“…This two-step etching process could give a fully hydrogenated surface and reduced the surface microroughness. 29 Then the cleaned Si wafers were immediately immersed into a growth solution with 3.09 M H 2 SiF 6 at 30°C for 5-12.5 min to grow initial LPD-SiOF films. After the deposition of 2-3 nm of LPD-SiOF films, wafers were annealed in an infrared furnace at 900°C using O 2 or N 2 O gas.…”

Characterization on the current-voltage curves of ultrathin silicon dioxides incorporated with fluorine and/or nitrogen

“…The Si cleaning processes were performed as follows: standard RCA clean, HF/H 2 O etching, H 2 O rinsed and HF/H 2 O etching again. This two-step etching process could give a fully hydrogenated surface and reduced the surface micro-roughness [24]. Then the cleaned Si wafers were immediately immersed into a growth solution with 3.09 M H 2 SiF 6 at 30 • C for 5-12.5 min to grow initial LPD-SiOF films.…”

Silicon Surface Morphology after Annealing in Ambient Hydrogen Containing a Trace Amount of Hydrogen Halide Gas

“…Thus, many researchers studied the microroughness of silicon surface in relation to various processes and characterizations, such as wet cleaning, [1][2][3] epitaxial growth, [4][5][6] rapid thermal processing, 7) removing photoresist, 8) silicon wafer bonding, 9) surface characterization, 10,11) and gate oxide integrity. [12][13][14][15][16] Various important devices necessary for information technology and power electronics are produced from the silicon epitaxial wafer. 17) Particularly, electronic power devices are expected to significantly decrease carbon dioxide emissions by optimizing the electric power transport while minimizing the power loss.…”