2005
DOI: 10.1016/j.microrel.2005.07.042
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Effect of test condition and stress free temperature on the electromigration failure of Cu dual damascene submicron interconnect line-via test structures

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Cited by 18 publications
(6 citation statements)
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“…Cu interconnect process was developed by IBM in 1985. Because it is difficult to etch for Cu, the double embedded technology, namely DD process, which includes oxidization, doping, deposition, printing, sputtering, electroplating, chemical mechanical polish (CMP), annealing and so on [31]. Photolithography is to carve micro holes and grooves on silica after precipitation.…”
Section: Trend Of Interconnect Processmentioning
confidence: 99%
“…Cu interconnect process was developed by IBM in 1985. Because it is difficult to etch for Cu, the double embedded technology, namely DD process, which includes oxidization, doping, deposition, printing, sputtering, electroplating, chemical mechanical polish (CMP), annealing and so on [31]. Photolithography is to carve micro holes and grooves on silica after precipitation.…”
Section: Trend Of Interconnect Processmentioning
confidence: 99%
“…From the AFD distributions for different SFT (see Figure 4.7), one can notice that AFD decreases with decrease in the SFT. Thus reducing SFT, AFD that exists at the beginning of EM test in the metallization can be reduced [90,92]. Since the failure time is inversely proportional to AFD as described earlier, one expects a similar trend between t 50 and 1/AFD.…”
Section: Resultsmentioning
confidence: 79%
“…It is to be noted here that failure site depends on the SFT as well as on the EM test condition [90,92]. Notice that the AFD distributions (see Figure 4.7) predict that for SFT in the range 360 to 340°C and when EM test condition are T=300°C, j=1…”
Section: Resultsmentioning
confidence: 81%
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