Effect of the Blocking Oxide Layer With Asymmetric Taper Angles in 3-D NAND Flash Memories

Abstract

The tapered channel effect is a major concern in three-dimensional (3-D) NAND technology because the effect causes differences in the electrical characteristics, including the threshold voltage (VT), between the upper and the lower cells. We simulated the tapered channel effect by using Sentaurus technology, computer-aided design (TCAD) tools, and based on the results, we propose a novel method to lessen the non-uniformity of the threshold voltage shift (∆VT) between the cells. The difference in ∆VT between the upper and the lower cells due to the tapered channel can be reduced by employing a tapered blocking oxide layer with a proper taper angle. These results will be helpful in designing reliable 3-D NAND flash memories. Index Terms-3-D NAND flash memories, threshold voltage shift, tapered channel

Investigation of Erase Cycling Induced Joint Dummy Cell Disturbance in Dual-Deck 3D NAND Flash Memory

“…The Vt distribution of the DMY0 at lower deck top position shifts higher than that of the DMY1 (at upper deck bottom position) after two erase pulses. Due to interference impact, the higher DMY0 Vt may impact the nearby WL Vt distribution such as WLn, which lead to WLn Vt disturbance [14][15][16][17].…”

Effect of Noncircular Channel on Distribution of Threshold Voltage in 3D NAND Flash Memory

“…While it has been possible to achieve etching of up to 128 layers, this technique encounters limitations when pushed beyond this threshold, primarily due to the constraints of available plasma etching methods. The management of the HAR etch process is a complex undertaking, and it introduces a spectrum of profile distortions, including tapering, center-line tilt, and warping [18][19][20][21][22][23][24]. Simultaneously, a microtrench structure frequently forms close to the bottom region of the tapered etch hole.…”