The tapered channel effect is a major concern in three-dimensional (3-D) NAND technology because the effect causes differences in the electrical characteristics, including the threshold voltage (VT), between the upper and the lower cells. We simulated the tapered channel effect by using Sentaurus technology, computer-aided design (TCAD) tools, and based on the results, we propose a novel method to lessen the non-uniformity of the threshold voltage shift (∆VT) between the cells. The difference in ∆VT between the upper and the lower cells due to the tapered channel can be reduced by employing a tapered blocking oxide layer with a proper taper angle. These results will be helpful in designing reliable 3-D NAND flash memories. Index Terms-3-D NAND flash memories, threshold voltage shift, tapered channel

Polymer light-emitting devices (PLEDs) with a MoO3 hole injection layer (HIL) were fabricated to enhance their luminance efficiency. Ultraviolet photoelectron spectroscopy spectra showed that the valence band maximum level of the MoO3 layer was located between the work function of the the indium-tin-oxide anode and the highest occupied molecular orbital level of the poly[N,N'-bis(4-butylphenyl)-N,N'-bis(phenyl)benzidine] hole transport layer. The surface of the MoO3 layer formed by using an ethanol solvent was smoother than that of the MoO layer formed by using a deionized water solvent due to a decrease in the aggregation of the MoO3 resolved in ethanol. The MO3 HIL decreased the operating voltage of the PLED and increased the luminance and the luminance efficiency of the PLED due to a decrease in the hole injection barrier. The operating voltage, the luminance, and the luminance efficiency of the PLEDs with the MoO3 HIL formed by using an ethanol solvent were enhanced in comparison with those of the PLEDs with a MoO3 HIL formed by using a deionized water solvent due to a decrease in the surface roughness of the HIL.

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Three-dimensional (3D) NAND flash memory devices having a poly-silicon channel with grain boundaries, the cylindrical macaroni channel being outside the inter-oxide filler layer and inside the tunneling oxide layer, were evaluated. The effects of the grain size, grain boundary trap density, and interface trap density at the interfaces between the channel and the oxide layers on the electrical characteristics of 3D NAND flash memory devices were investigated. The electron density of the channel was changed depending on the grain boundary trap density and the position of the grain boundary trap in the channel. The grain boundary traps increased the potential barrier and decreased the electron density of the channel. The threshold voltage increased with increasing grain boundary trap density and interface trap density.

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