Effect of the Dummy Gate on the Capacitance Characteristics of the LDMOSFETs

Zhu, Congyi; Fu, Jun; Wang, Yudong; Liu, Zhihong; Wu, Zheng; Xu, Ping; Cui, Jie; Jiang, Zhi yu; Zhao, Yue; Zhang, Zhaojian

doi:10.1149/1.3360604

RF MOSFETs

Kumari,

Gupta,

Saxena

2024

Encyclopedia of RF and Microwave Engineering

0

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In this article, the RF performance of different MOSFET architectures such as Silicon‐On‐Insulator (SOI), Lightly Doped Drain (LDD) MOSFET, Graphene FET, and Negative Capacitance (NC) FET have been reported based on the previously reported work in the form of equivalent circuits. Using the data reported in the literature, the cutoff frequency and maximum frequency of oscillation have been summarized with varying channel lengths. Compared results show that multigate architecture results in higher cutoff frequency and a maximum frequency of oscillation, which can be further increased by decreasing the channel length of the MOSFET architecture. However, the deterioration in the resulting device gain at lower channel length has also been reported. Furthermore, the performance of SOI, Silicon‐on‐Nothing (SON), Double Gate (DG), Double‐Gate Silicon‐On‐Insulator (DGSOI), and Empty Space in Double‐Gate (ESDG) architectures have been explored using ATLAS TCAD software tool for RF and digital parameters investigation. The various parameters explored in this article are current density, electric field, breakdown voltage, impact ionization rate, scattering parameters, noise conductance, minimum noise figure, and cross‐correlation factor. The presented results show that, for the same drain current value, ESDG architecture has higher device gain compared to other devices used for comparison along with higher cutoff frequency. However, this higher device gain comes at the cost of a slightly higher minimum noise figure but with improved noise conductance and cross‐correlation factor (slightly higher than DG). Thus, ESDG is a reliable candidate for LNA design compared to other devices.

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RF MOSFETs

Kumari,

Gupta,

Saxena

2024

Encyclopedia of RF and Microwave Engineering

0

View full text Add to dashboard Cite

In this article, the RF performance of different MOSFET architectures such as Silicon‐On‐Insulator (SOI), Lightly Doped Drain (LDD) MOSFET, Graphene FET, and Negative Capacitance (NC) FET have been reported based on the previously reported work in the form of equivalent circuits. Using the data reported in the literature, the cutoff frequency and maximum frequency of oscillation have been summarized with varying channel lengths. Compared results show that multigate architecture results in higher cutoff frequency and a maximum frequency of oscillation, which can be further increased by decreasing the channel length of the MOSFET architecture. However, the deterioration in the resulting device gain at lower channel length has also been reported. Furthermore, the performance of SOI, Silicon‐on‐Nothing (SON), Double Gate (DG), Double‐Gate Silicon‐On‐Insulator (DGSOI), and Empty Space in Double‐Gate (ESDG) architectures have been explored using ATLAS TCAD software tool for RF and digital parameters investigation. The various parameters explored in this article are current density, electric field, breakdown voltage, impact ionization rate, scattering parameters, noise conductance, minimum noise figure, and cross‐correlation factor. The presented results show that, for the same drain current value, ESDG architecture has higher device gain compared to other devices used for comparison along with higher cutoff frequency. However, this higher device gain comes at the cost of a slightly higher minimum noise figure but with improved noise conductance and cross‐correlation factor (slightly higher than DG). Thus, ESDG is a reliable candidate for LNA design compared to other devices.

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An analytical model for the drain—source breakdown voltage of RF LDMOS power transistors with a Faraday shield

Zhang

¹

,

Zhang

²

,

Fu

³

et al. 2012

J. Semicond.

Self Cite

2

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An analytical model for the drain—source breakdown voltage of an RF LDMOS power transistor with a Faraday shield is derived on the basis of the solution of the 2D Poisson equation in a p-type epitaxial layer, as well as an n-type drift region by means of parabolic approximation of electrostatic potential. The model captures the influence of the p-type epitaxial layer doping concentration on the breakdown voltage, compared with the previously reported model, as well as the effect of the other device parameters. The analytical model is validated by comparing with a numerical device simulation and the measured characteristics of LDMOS transistors. Based on the model, optimization of LDMOS device parameters to achieve proper trade-off between the breakdown voltage and other characteristic parameters such as on-resistance and feedback capacitance is analyzed.

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Effect of the Dummy Gate on the Capacitance Characteristics of the LDMOSFETs

Cited by 4 publications

References 5 publications

RF MOSFETs

RF MOSFETs

RF MOSFETs

An analytical model for the drain—source breakdown voltage of RF LDMOS power transistors with a Faraday shield

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