Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure

Abstract

Metal Oxide Semiconductor (MOS) capacitors (MOSCAP) have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer), time-temperature cycle and sequence are key parameters influencing the device’s output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application.

Electrical Characterization of Postmetal Annealed Ultrathin TiN Gate Electrodes in Si MOS Capacitors

“…The deposition of both the high-k dielectric HfSiO layer and 1.5 nm TiN metal gate was accomplished with Atomic Layer Deposition system. Details of ALD parameters are reported elsewhere [14]. The deposition chamber was preheated at 315 ∘ C. A high-k dielectric layer is deposited on Si (100) wafers by injecting the Hf and Si liquid precursors one by one.…”

Gate-Stack Engineering to Improve the Performance of 28 nm Low-Power High-K/Metal-Gate Device

“…Compared to the POR fabrication method, the enhanced device performance achieved with the new fabrication method can be judged to be the main reason for the gain by considering the mobility, as discussed in [ 7 ]. The better quality of the HfSiO film leads to better I on / I off than that achieved with the HfSiON film if there is no problem with the risk from the heat budget covered in the previous study [ 18 ].…”