Effect of TSV interposer on the thermal performance of FCBGA package

Abstract

In this paper, the effect of TSV (Through Silicon Via) parameters on the equivalent thermal conductivity of TSV interposer and the effect of the TSV interposer on the thermal performance of the package have been elaborated. The modeling approach using in this paper includes compact modeling for the package and detailed modeling for the TSV interposer. The objective of compact modeling is to study the effect of TSV interposer on thermal performance of the package, while the objective of detailed modeling is to extract the equivalent thermal conductivity of TSV interposer which is used for compact modeling. The proposed package in this study includes a large die with fine pitch, a silicon interposer with TSV, a 1-2-1 buildup substrate and a PCB board. In addition, to evaluate the thermal performance of the proposed package, a similar package without the TSV interposer is also modeled in this study for comparison. The results of detailed modeling show that the equivalent thermal conductivity of TSV interposer can be increased by reducing the pitch and via ratio of TSV, as well as increasing the plating thickness of partial filled TSV and using highly conductive filler material. Furthermore, the results of compact modeling reveal that the proposed TSV interposer improves the thermal performance of the package. The thermal resistance of the package decreases when the interposer size and thickness increase, and the equivalent thermal conductivity of TSV interposer has negligible effect on thermal performance of the package.

Heterogeneous 2.5D integration on through silicon interposer

“…Without compromising processing speed, the integration of multi-chips in one interposer on the package tends to generate higher heat density, which needs to be addressed in the 2.5D or 3D package design. [102][103][104][105][106][107][108][109][110][111][112][113][114][115] A schematic of the cooling concepts is illustrated in Figure 50.…”

“…The approach for extracting the equivalent thermal conductivity is shown in Figure 51 for modeling of equivalent thermal conductivities of TSV interposer along the through plane z direction and in-plane x and y directions. 109 First, create the geometry of TSV interposer with different TSV design parameters, then set the boundary conditions and simulate the temperature distribution. After obtaining the temperature distribution, the equivalent thermal conductivity can be calculated.…”

Experimental demonstration of the effect of copper TPVs (Through package vias) on thermal performance of glass interposers

“…Recent simulations have reported the favorable effect of copper Through-Silicon-Vias (TSVs) on thermal performance of silicon interposers for Flip Chip Ball Grid Array (FCBGA) package [3], network system application [4], and 3D IC integration [5]. Thermal influence of the array density of TSVs, and the proximity to a heat source have been studied through modeling, and validated through experiments by using back-end-of-line (BEOL) structures [6].…”

Thermal evaluation and analyses of 3D IC integration SiP with TSVs for network system applications

“…Thermal management is one of the critical issues of 3D IC integration [11][12][13][14][15][16][17][18][19][20][21]. This is because: (1) the heat generated by stacked multifunctional chips in miniature packages is quite high; (2) 3D IC increase the net heat flux that must be dissipated via per unit surface area of package; (3) enclosed chips in the 3D IC package may be easily overheated if the accumulated heat is not properly drained away; (4) the space between the 3D stack may be too small for cooling channels (i.e., no gap for fluid flow); and (5) thinner chips may create more extreme conditions for on-chip hot spots.…”