Effect of wafer defects on electrical properties and yields of SiC Devices

Li, Ling; Yan, Hai-liang; Li, Jialin; Li, Qingling; Zhu, Tao; Wu, Hao; Li, Rui; Jin, Rui; Wu, Junmin

doi:10.1088/1742-6596/2033/1/012095

Cited by 4 publications

(4 citation statements)

References 3 publications

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Section: Impact Of Defects On Devicesmentioning

confidence: 99%

“…In MOSFET, BPDs increase on-resistance [91] and reduce the gate oxide reliability [92]. Micropipes limit the operation current and increase the leakage current [93,94] while defects such as SFs, carrots and polytype inclusions reduce blocking voltage [4,91] and scratches on the surface cause reliability issues [95]. Isshiki et al show that there are latent scratches, consisting of complex stacking faults and dislocation loops lying beneath the SiC substrate, resulting in formation of step bunching and degradation of dielectric strength of oxide film in SiC-MOSFETs [79].…”

Section: Impact Of Defects On Devicesmentioning

confidence: 99%

“…In a p-n diode, BPDs increase the on-resistance and leakage current [91] while TSDs and TEDs reduce blocking voltage [104]. Micropipes limit the operation current and increase the leakage current [93,94] while SFs increase forward voltage [105].…”

Section: Impact Of Defects On Devicesmentioning

confidence: 99%

“…5. As one can see, defects can deteriorate the device characteristics in many ways [91,117]. Although the negative effects of defects can be counteracted by designing different device structures [1][2][3][118][119][120][121][122][123], establishing a fast and accurate defect inspection system is amid a pressing need to help one observe defects and further optimize the process to reduce them.…”

Section: Impact Of Defects On Devicesmentioning

confidence: 99%

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Defect Inspection Techniques in SiC

et al. 2022

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With the increasing demand of silicon carbide (SiC) power devices that outperform the silicon-based devices, high cost and low yield of SiC manufacturing process are the most urgent issues yet to be solved. It has been shown that the performance of SiC devices is largely influenced by the presence of so-called killer defects, formed during the process of crystal growth. In parallel to the improvement of the growth techniques for reducing defect density, a post-growth inspection technique capable of identifying and locating defects has become a crucial necessity of the manufacturing process. In this review article, we provide an outlook on SiC defect inspection technologies and the impact of defects on SiC devices. This review also discusses the potential solutions to improve the existing inspection technologies and approaches to reduce the defect density, which are beneficial to mass production of high-quality SiC devices.

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Section: Impact Of Defects On Devicesmentioning

confidence: 99%

Section: Impact Of Defects On Devicesmentioning

confidence: 99%

Section: Impact Of Defects On Devicesmentioning

confidence: 99%

Section: Impact Of Defects On Devicesmentioning

confidence: 99%

See 2 more Smart Citations

Defect Inspection Techniques in SiC

et al. 2022

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Relationship between the kernel size of a convolutional layer and the optical point spread function in ghost imaging using deep learning for identifying defect locations

et al. 2022

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We explore the contribution of convolutional neural networks to correcting for the effect of the point spread function (PSF) of the optics when applying ghost imaging (GI) combined with deep learning to identify defect positions in materials. GI can be accelerated by combining GI and deep learning. However, no method has been established for determining the relevant model parameters. A simple model with different kernel sizes was built. Its accuracy was evaluated for data containing the effects of different PSFs. Numerical analysis and empirical experiments demonstrate that the accuracy of defect identification improved by matching the kernel size with the PSF of the optics.

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Noise-robust deep learning ghost imaging using a non-overlapping pattern for defect position mapping

Kataoka¹,

Mizutani²,

Uenohara³

et al. 2022

Appl. Opt.

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Defect detection requires highly sensitive and robust inspection methods. This study shows that non-overlapping illumination patterns can improve the noise robustness of deep learning ghost imaging (DLGI) without modifying the convolutional neural network (CNN). Ghost imaging (GI) can be accelerated by combining GI and deep learning. However, the robustness of DLGI decreases in exchange for higher speed. Using non-overlapping patterns can decrease the noise effects in the input data to the CNN. This study evaluates the DLGI robustness by using non-overlapping patterns generated based on binary notation. The results show that non-overlapping patterns improve the position accuracy by up to 51%, enabling the detection of defect positions with higher accuracy in noisy environments.

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Effect of wafer defects on electrical properties and yields of SiC Devices

Cited by 4 publications

References 3 publications

Defect Inspection Techniques in SiC

Defect Inspection Techniques in SiC

Relationship between the kernel size of a convolutional layer and the optical point spread function in ghost imaging using deep learning for identifying defect locations

Noise-robust deep learning ghost imaging using a non-overlapping pattern for defect position mapping

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