Effective and Efficient Test Pattern Generation for Small Delay Defect

Goel, Sandeep; Devta-Prasanna, Narendra; Turakhia, R.

doi:10.1109/vts.2009.28

Cited by 44 publications

(6 citation statements)

References 11 publications

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“…Girard et al [11] adopted the method of critical path tracing in delay fault diagnosis. According to the different methods of processing timing information, small-delay fault simulation can be classified into two categories: path-based simulation [2][3][4][5][6] and waveform-based simulation [14][15][16]. Li et al [13] extended the application of GPU and critical path tracing for transition fault simulation.…”

Section: Introductionmentioning

confidence: 99%

“…Recently, many methods aimed at small-delay detection have been presented, such as faster-than-at-speed test [2], timing-aware based automatic test pattern generator (ATPG) [3,4], and pattern selection based on an N-detect transition fault (TF) test repository [5,6]. These methods achieved a higher small-delay test quality.…”

Section: Introductionmentioning

confidence: 99%

“…However, to be different from stuck-at fault and transition fault, the simulation of SDD needs to take into account timing information. According to the different methods of processing timing information, small-delay fault simulation can be classified into two categories: path-based simulation [2][3][4][5][6] and waveform-based simulation [14][15][16]. In the path-based simulation, every sensitized path is calculated, and the fault detection is determined by the longest path running through the target fault site.…”

Section: Introductionmentioning

confidence: 99%

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An efficient small‐delay faults simulator based on critical path tracing

Liu

Kuang

Cai

et al. 2014

Circuit Theory & Apps

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Testing for small-delay defects (SDDs) has become an important component of integrated circuit testing. In this paper, an efficient small-delay fault simulator, a hybrid method combining forward serial simulation and backward critical path tracing simulation for SDDs is proposed, which aims to determine the coverage of small-delay defects for a given test set fast and accurately. In our proposed method, a unit delay model is employed, and reconvergent sensitization as well as hazard-based detection is considered. Signal waveforms are expressed by bitmap data forms. In addition to providing an accurate result for fault simulation, the proposed simulator can well assist test generation. Experimental results demonstrate that the proposed simulator can further accelerate the simulation by one or two orders of magnitude compared with previous works.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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An efficient small‐delay faults simulator based on critical path tracing

Liu

Kuang

Cai

et al. 2014

Circuit Theory & Apps

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“…Different approaches can be found in the literature, for example [18], targeting industrial benchmarks, and the one in [19], selecting the most efficient patterns from timing-unaware ATPG tools and working on IWLS 2005 benchmarks circuits. Approaches for the identification of the longest paths through a fault site, which are crucial for SDD tests, are proposed in [20] and [21].…”

Section: Related Workmentioning

confidence: 99%

An effective approach to automatic functional processor test generation for small-delay faults

Riefert

Ciganda

Sauer

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Functional microprocessor test methods provide several advantages compared to DFT approaches, like reduced chip cost and at-speed execution. However, the automatic generation of functional test patterns is an open issue.In this work we present an approach for the automatic generation of functional microprocessor test sequences for small-delay faults based on Bounded Model Checking. We utilize an ATPG framework for small-delay faults in sequential, non-scan circuits and propose a method for constraining the input space for generating functional test sequences (i.e., test programs). We verify our approach by evaluating the miniMIPS microprocessor. In our experiments we were able to reach over 97 % fault efficiency.To the best of our knowledge, this is the first fully automated approach to functional microprocessor test for small-delay faults.

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“…It is based on robust path delay test and attempts to find the longest sensitizable paths passing through the target fault site and generating a slow-to-rise or slow-to-fall transition. The authors in [2] proposed a hybrid method using 1-detect and timingaware ATPGs to detect SDDs based on SDF with a reduced pattern count. In [3], a static-timing-analysis based method was proposed to generate and select patterns that sensitize long paths.…”

Section: A Related Prior Workmentioning

confidence: 99%

High-quality pattern selection for screening small-delay defects considering process variations and crosstalk

Peng

Yilmaz

Tehranipoor

et al. 2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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Abstract-Testing for small-delay defects (SDDs) is necessary to ensure the quality and reliability of high-performance integrated circuits fabricated with the latest technologies. These timing defects can be caused by process variations, crosstalk, and power-supply noise, as well as by physical defects such as resistive opens and shorts. Timing-aware ATPG tools have been developed for SDD detection. However, they only use static timing analysis reports for path-length calculation and neglect important parameters such as process variations, crosstalk, and powersupply noise, which can induce small delays into the circuit and impact the timing of targeted paths. In this paper, we present an efficient pattern evaluation and selection procedure for screening SDDs that are caused by physical defects and by delays added to paths by process variations and crosstalk. In this procedure, the best patterns for SDDs are selected from a large repository test set. Experimental results demonstrate that our method sensitizes more long paths and detects more SDDs with a much smaller pattern count compared with a commercial timing-aware ATPG tool.

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Effective and Efficient Test Pattern Generation for Small Delay Defect

Cited by 44 publications

References 11 publications

An efficient small‐delay faults simulator based on critical path tracing

An efficient small‐delay faults simulator based on critical path tracing

An effective approach to automatic functional processor test generation for small-delay faults

High-quality pattern selection for screening small-delay defects considering process variations and crosstalk

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