Effective approach to enhance DC and high‐frequency performance of electrically doped TFET

Yadav, Shivendra; Lemtur, Alemienla; Sharma, Dheeraj; Aslam, Mohd.; Soni, Deepak

doi:10.1049/mnl.2018.5072

Cited by 12 publications

(15 citation statements)

References 18 publications

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“…Device structure consists of two isolated gates separated from each other by 5 nm, named as control gate (CG) and polarity gate (PG). To convert the

N^{+} - N^{+} - N^{+}

substrate region into the

N^{+} - I - P^{+}

region, metals with work functions 4.3 eV (aluminium) and 5.93 eV (platinum) are used for the electrodes of CG and PG, respectively, which results into the formation of a JL‐TFET [5, 22–29]. Also, to improve the reliability of the JL‐TFET, stack of gate oxide

(Si O_{2} + Hf O_{2} false)

has been used instead of single layer of

Si O_{2}

[22].…”

Section: Device Structure and Simulation Setupmentioning

confidence: 99%

“…LWLS is comprised of two metal strips: one is oriented vertically and other horizontally. The horizontal LWLS is connected to the gate electrode via vertical LWLS [24]. LWLS can be fabricated using molybdenum (Mo), because Mo is a very flexible metal and is known to have work function ranging from 3.8 to 5 eV simply by implanting nitrogen [24, 25].…”

Section: Device Structure and Simulation Setupmentioning

confidence: 99%

“…Shockley–Read–Hall and Auger recombination models have also employed to see minority recombination effects [5, 26]. High doping concentration results in narrow bandgap in a semiconductor; therefore, to consider this effect, bandgap narrowing model is enabled [4, 24]. Concentration‐dependent mobility model and field‐dependent mobility model are also invoked to account the effects of different doping concentrations and electric fields on the carrier mobilities [30].…”

Section: Device Structure and Simulation Setupmentioning

confidence: 99%

“…Thus, the created device is named as SGO‐JL double‐gate TFET with low work‐function LWLS‐SGO‐JL‐TFET. The fabrication of the device can be performed using the techniques similar to reported in [23, 24]. Temperature sensitivity of a device provides the impacts of temperature variation on its electrical behaviour.…”

Section: Introductionmentioning

confidence: 99%

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Temperature sensitivity analysis of SGO metal strip JL TFET

Nigam

Kumar

Singh

et al. 2020

IET Circuits, Devices & Systems

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Temperature sensitivity is one of the major concern in conventional stacked gate-oxide junctionless tunnel-field-effect transistor (SGO-JL-TFET). In this regard, the authors have investigated the sensitivity toward the temperature variation of the SGO-JL double-gate TFET with low work-function live strip (LWLS-SGO-JL-TFET) and without LWLS-SGO-JL-TFET (SGO-JL-TFET). Furthermore, they have analysed and compared the impact of operating temperature variation on the DC, analogue/ radiofrequency and linearity performances of both the devices with the help of simulation results obtained using technology computer-aided design tool. It can be stated that the proposed device is less sensitive toward the temperature variation in terms of carrier concentration, electric field, on-state current and off-state current, as compared with conventional SGO-JL-TFET. Apart from these parameters, proposed device also demonstrates better temperature sensitivity in terms of analogue performance parameters such as transconductance (g m) cutoff frequency (f T), gain bandwidth product and maximum oscillating frequency (f max). Therefore, the proposed device can be a potential candidate for cryogenics and high-temperature applications.

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“…Device structure consists of two isolated gates separated from each other by 5 nm, named as control gate (CG) and polarity gate (PG). To convert the

N^{+} - N^{+} - N^{+}

substrate region into the

N^{+} - I - P^{+}

(Si O_{2} + Hf O_{2} false)

has been used instead of single layer of

Si O_{2}

[22].…”

Section: Device Structure and Simulation Setupmentioning

confidence: 99%

Section: Device Structure and Simulation Setupmentioning

confidence: 99%

Section: Device Structure and Simulation Setupmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Temperature sensitivity analysis of SGO metal strip JL TFET

Nigam

Kumar

Singh

et al. 2020

IET Circuits, Devices & Systems

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“…A TFET can deliver the SS values smaller than that of a conventional MOSFET (

\sim

60 mV/decade at room temperature) [1]. In the recent past, several research efforts have been made to improve the performance of TFETs [5–13]. Despite the excellent switching performance and reduced

I_{normalOFF}

, the TFETs suffer from low ON‐state current (

I_{normalON}

) which restricts the use of TFETs for commercial applications.…”

Section: Introductionmentioning

confidence: 99%

Dual‐channel trench‐gate tunnel FET for improved ON‐current and subthreshold swing

Joshi

Singh

2019

Electron. lett.

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In this Letter, a dual-channel trench-gate tunnel field-effect transistor (DCTG-TFET) is proposed and investigated. The gate of DCTG-TFET is placed vertically in a trench to create two channels which carry drain current in parallel. The proposed device dimensions are optimised to reduce channel resistance and tunnelling width for an appreciable increase in the ON-state current (I ON). The performance of DCTG-TFET is analysed using two-dimensional simulations in the device simulator. The proposed DCTG-TFET provides one order of magnitude improvement in I ON /I OFF current ratio and 17 times reduction in subthreshold swing as compared to recently reported two-source-region tunnel field-effect transistor structure.

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