2013
DOI: 10.7567/jjap.52.04ca02
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Effective Work Function Engineering for Aggressively Scaled Planar and Multi-Gate Fin Field-Effect Transistor-Based Devices with High-k Last Replacement Metal Gate Technology

Abstract: This work reports on aggressively scaled replacement metal gate, high-k last devices (RMG-HKL), exploring several options for effective work function (EWF) engineering, and targeting logic high-performance and low-power applications. Tight low-threshold voltage (V T) distributions for scaled NMOS devices are obtained by controlled TiN/TiAl-alloying, either by using RF-physical vapor deposition (RF-PVD) or atomic layer deposition (ALD) for TiN growth. The first technique allows optimization of… Show more

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Cited by 16 publications
(20 citation statements)
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“…Using TiAl as an Al diffusion source, low TiN work function values around 4.1-4.2 eV can be expected. 10 The extracted TiN EWF from TiN/TiAl devices with 5 nm of TiAl was 3.96 eV, while for the same metal gate stack with 2 nm of TiAl the TiN EWF value was about 4.13 eV. Literature reports that a reduction of 0.60 eV on TiN EWF can be achieved using TiAl layer, 10 the Al dif.…”
Section: Resultsmentioning
confidence: 98%
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“…Using TiAl as an Al diffusion source, low TiN work function values around 4.1-4.2 eV can be expected. 10 The extracted TiN EWF from TiN/TiAl devices with 5 nm of TiAl was 3.96 eV, while for the same metal gate stack with 2 nm of TiAl the TiN EWF value was about 4.13 eV. Literature reports that a reduction of 0.60 eV on TiN EWF can be achieved using TiAl layer, 10 the Al dif.…”
Section: Resultsmentioning
confidence: 98%
“…Solutions for the nMOS EWF in the range of 4.1-4.4 eV can be obtained by doping the TiN film with different materials (such as Al and N). [8][9][10] Literature reports had shown that the addition of Al ions into TiN layer can significantly change the TiN EWF. 8,10 The metal gate EWF shift is related to formation of different dipoles at the interface between metal gate and high-k due Al diffusion.…”
Section: Introductionmentioning
confidence: 99%
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“…One wafer received a post-HfO 2 -ALD 9 min SF 6 -plasma exposure to introduce F in the gate stack. This was followed by a 1 min anneal in N 2 at 500 o C [10]. One reference wafer did not receive a post-high-k treatment, while wafer 5 received a post-HfO 2 -ALD heat treatment.…”
Section: Methodsmentioning
confidence: 99%