Effects of a trench under the gate in high voltage RESURF LDMOSFET for SOI power integrated circuits

A new silicon-on-insulator (SOI) power lateral MOSFET with a dual vertical field plate (VFP) in the oxide trench is proposed. The dual VFP modulates the distribution of the electric field in the drift region, which enhances the internal field of the drift region and increases the drift doping concentration of the drift region, resulting in remarkable improvements in breakdown voltage (BV) and specific on-resistance (R on,sp ). The mechanism of the VFP is analyzed and the characteristics of BV and R on,sp are discussed. It is shown that the BV of the proposed device increases from 389 V of the conventional device to 589 V, and the R on,sp decreases from 366 mΩ•cm 2 to 110 mΩ•cm 2 .

Section: Device Structure and Mechanismmentioning

confidence: 89%

Section: Introductionmentioning

confidence: 99%

High-voltage SOI lateral MOSFET with a dual vertical field plate

Fan¹,

Zhang²,

Luo³

et al. 2013

“…[6,7] The oxide trench in the drift region can decrease the high electric field near the gate and increase length of ionization integral, resulting in a high BV and mini cell pitch. [8][9][10] However, it is still difficult to obtain the satisfactory result in present oxide trench devices.…”

Section: Introductionmentioning

confidence: 99%

Improving breakdown voltage performance of SOI power device with folded drift region

Pingjiang

et al. 2016

A novel silicon-on-insulator (SOI) high breakdown voltage (BV) power device with interlaced dielectric trenches (IDT) and N/P pillars is proposed. In the studied structure, the drift region is folded by IDT embedded in the active layer, which results in an increase of length of ionization integral remarkably. The crowding phenomenon of electric field in the corner of IDT is relieved by the N/P pillars. Both traits improve two key factors of BV, the ionization integral length and electric field magnitude, and thus BV is significantly enhanced. The electric field in the dielectric layer is enhanced and a major portion of bias is borne by the oxide layer due to the accumulation of inverse charges (holes) at the corner of IDT. The average value of the lateral electric field of the proposed device reaches 60 V/µm with a 10 µm drift length, which increases by 200% in comparison to the conventional SOI LDMOS, resulting in a breakdown voltage of 607 V.

“…[4][5][6][7] A dielectric trench inserted in the drift region for LDMOS not only improves the BV , but also dramatically reduces the R on,sp by shortening the device cell pitch. [8][9][10][11] However, a conventional deep trench is not suitable for high voltage application (e.g. BV > 600 V) because of its weakened RESURF effect and a corresponding low N d .…”

Section: Introductionmentioning

confidence: 99%

An ultra-low specific on-resistance trench LDMOS with a U-shaped gate and accumulation layer

Li¹,

Luo²,

Luo³

et al. 2015

An ultra-low specific on-resistance (R on,sp ) oxide trench-type silicon-on-insulator (SOI) lateral double-diffusion metal-oxide semiconductor (LDMOS) with an enhanced breakdown voltage (BV ) is proposed and investigated by simulation. There are two key features in the proposed device: one is a U-shaped gate around the oxide trench, which extends from source to drain (UG LDMOS); the other is an N pillar and P pillar located in the trench sidewall. In the on-state, electrons accumulate along the U-shaped gate, providing a continuous low resistance current path from source to drain. The R on,sp is thus greatly reduced and almost independent of the drift region doping concentration. In the off-state, the N and P pillars not only enhance the electric field (E-field) strength of the trench oxide, but also improve the E-field distribution in the drift region, leading to a significant improvement in the BV . The BV of 662 V and R on,sp of 12.4 mΩ•cm 2 are achieved for the proposed UG LDMOS. The BV is increased by 88.6% and the R on,sp is reduced by 96.4%, compared with those of the conventional trench LDMOS (CT LDMOS), realizing the state-of-the-art trade-off between BV and R on,sp .