Effects of BEOL copper CMP process on TDDB for direct polishing ultra-low k dielectric cu interconnects at 28nm technology node and beyond

Hsieh, Yi-Lin; Lin, Wen-Chin; Lin, Yu Min; Hsu, H. K.; Chen, C. H.; Tsao, W. C.; Hsu, Chia Wei; Huang, Rao; Lin, C.-H.; Su, Yan-Kuin; Kangwei, Liu,; Huang, Chien Chung; Wu, J. Y.

doi:10.1109/irps.2013.6532056

Cited by 10 publications

(3 citation statements)

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“…Poor reliability performance is obtained when using unsuitable polishing slurries and post-CMP cleaning solutions. [64][65][66] As suggested by Izumitani et al, 67 porosity increase influences the film resistance to CMP damage. CMP interface quality degradation involves three concerns: dangling bonds generation, metal contaminants and moisture presence.…”

Section: Reliability After Integrationmentioning

confidence: 88%

Electrical Reliability Challenges of Advanced Low-k Dielectrics

Baklanov

et al. 2014

ECS J. Solid State Sci. Technol.

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We review the latest studies that address the fundamental understanding of low-k dielectric electrical properties and reliability. We focus on the results discussing the nature of process induced defects, leakage currents and breakdown behavior, as they are important factors to reveal material modification and damage. Issues related to the use of porogen based PECVD techniques during dielectric deposition are discussed, where we focus on the selection of matrix and porogen precursors and on the improvements related to post-deposition treatments. During damascene integration, low-k dielectrics are subjected to several processes that induce material damage, where we review recent learning about plasma exposure, barrier deposition and chemical mechanical polishing. In order to have a successful implementation of advanced ultralow-k films in back-end-of-line interconnects, we argue that more research efforts are needed with respect to its material development, integration and reliability and make some proposals for future work. The development and integration of reliable low-k materials is a key challenge for next generation interconnect technologies. Driven by the requirement of performance increase, highly porous low-k dielectrics are incorporated in deeply scaled back-end-of-line (BEOL) interconnects. In general, there are three important concerns during the study of low-k dielectric electrical properties and reliability: a) the k-value of the dielectric after integration should maintain relatively unchanged, b) the leakage current of the dielectric between metal lines should be low, and c) the time dependent dielectric breakdown (TDDB) failure time of the integrated BEOL structure at operating conditions should meet its specifications. 1Porous SiOCH low-k dielectrics deposited by plasma enhanced chemical vapor deposition (PECVD) techniques are the dominant choice for k>2.2 film depositions and are also potential candidates for ultralow-k (k<2.2) dielectric applications.2 In the past years, significant efforts have been spent to understand their material properties and integration challenges. The bond structures of low-k dielectrics is complex due to the non-equilibrium nature of the PECVD technique.

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Section: Reliability After Integrationmentioning

confidence: 88%

Electrical Reliability Challenges of Advanced Low-k Dielectrics

Baklanov

et al. 2014

ECS J. Solid State Sci. Technol.

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“…For the CMP of different materials, or ultra-thin film CMP, multi-layer heterogeneous integrated CMP, even the formation of dozens of integrated circuit structures began to be introduced into integrated circuit manufacturing, while the introduction of EUV and the step-by-step approach to nanoscale processes are getting closer to the limits of precision process technology. Therefore, a series of technologies that help improve the manufacturing yield of integrated circuits, such as layout design and manufacturing process improvement and manufacturability design, have a long time to find a clearer CMP mechanism and model in different application scenarios [27][28][29][30][31][32].…”

Section: Resultsmentioning

confidence: 99%

Review on modeling and application of chemical mechanical polishing

Zhao

Wei

Wang

et al. 2020

Nanotechnology Reviews

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AbstractWith the development of integrated circuit technology, especially after entering the sub-micron process, the reduction of critical dimensions and the realization of high-density devices, the flatness between integrated circuit material layers is becoming more and more critical. Because conventional mechanical polishing methods inevitably produce scratches of the same size as the device in metal or even dielectric layers, resulting in depth of field and focus problems in lithography. The first planarization technique to achieve application is spin on glass (SOG) technology. However, this technology will not only introduce new material layers, but will also fail to achieve the global flattening required by VLSI and ULSI technologies. Moreover, the process instability and uniformity during spin coating do not meet the high flatness requirements of the wafer surface. Also, while some techniques such as reverse etching and glass reflow can achieve submicron level regional planarization. After the critical dimension reaches 0.35 microns (sub-micron process), the above methods cannot meet the requirements of lithography and interconnect fabrication. In the 1980s, IBM first introduced the chemical mechanical polishing (CMP) technology used to manufacture precision optical instruments into its DRAM manufacturing [1]. With the development of technology nodes and critical dimensions, CMP technology has been widely used in the Front End Of Line (FEOL) and Back End Of Line (BEOL) processes [2]. Since the invention of chemical mechanical polishing, scientists have not stopped studying its internal mechanism. From the earliest Preston Formula (1927) to today’s wafer scale, chip scale, polishing pad contact, polishing pad - abrasive - wafer contact and material removal models, there are five different scale models from macro to the micro [3]. Many research methods, such as contact mechanics, multiphase flow kinetics, chemical reaction kinetics, molecular dynamics, etc., have been applied to explain the principles of chemical mechanical polishing to establish models. This paper mainly introduces and summarizes the different models of chemical mechanical polishing technology. The various application scenarios and advantages and dis-advantages of the model are discussed, and the development of modeling technology is introduced.

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“…Additionally, void formation during metal fill in highly scaled trenches and via holes during the dual-damascene (DD) process [ Fig. 2(a)] exacerbates the reliability and variability problems [9]- [11]. Owing to its excellent electrical [12], [13], optical [14], [15], and thermo-electric [16], [17] properties, graphene [or more specifically doped multilayer graphene (DMLG)] was first proposed by Xu et al [18] as a promising solution to various interconnect scaling challenges, and was theoretically shown to beat the resistivity and performance of sub-20 nm Cu by appropriate level of doping (by intercalation) [8].…”

mentioning

confidence: 99%

Demonstration of CMOS-Compatible Multi-Level Graphene Interconnects With Metal Vias

Agashiwala

Jiang

Parto

et al. 2021

IEEE Trans. Electron Devices

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Doped-multilayer-graphene (DMLG) interconnects employing the subtractive-etching (SE) process have opened a new pathway for designing interconnects at advanced technology nodes, where conventional metal wires suffer from significant resistance increase, selfheating (SH), electromigration (EM), and various integration challenges. Even though single-level scaled graphene wires have been shown to possess better performance and reliability with respect to dual-damascene (DD) and SE-enabled metal wires, a multi-level graphene interconnect technology (with vias) has remained elusive, which is of paramount importance for its integration in future technology nodes. This work, for the first time, addresses that need by engineering a CMOS-compatible solid-phase growth technique to yield large-area multilayer graphene (MLG) on dielectric (SiO 2) and metal (Cu) substrates and subsequently demonstrating multi-level MLG interconnects with metal vias. Using rigorous theoretical and experimental analyses, we demonstrate that multi-level MLG interconnects with metal vias undergo < 2% change in the via resistance under accelerated stress conditions, demonstrating its superior reliability against SH and EM, making them ideal candidates for sub-10 nm nodes.

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Effects of BEOL copper CMP process on TDDB for direct polishing ultra-low k dielectric cu interconnects at 28nm technology node and beyond

Cited by 10 publications

References 1 publication

Electrical Reliability Challenges of Advanced Low-k Dielectrics

Electrical Reliability Challenges of Advanced Low-k Dielectrics

Review on modeling and application of chemical mechanical polishing

Demonstration of CMOS-Compatible Multi-Level Graphene Interconnects With Metal Vias

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