Effects of Contact Potential and Sidewall Surface Plane on the Performance of GaN Vertical Nanowire MOSFETs for Low-Voltage Operation

Abstract

HAL is a multi-disciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L'archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d'enseignement et de  Abstract--GaN-based materials are expected to show excellent immunity against short-channel effects because they have relatively lower permittivity and higher electron effective mass, compared to other materials such as Si, Ge, and In(Ga)As. To further reduce the short-channel effects, it is important to enhance the gate controllability of the device by utilizing a gateall-around structure. In this work, GaN vertical GAA nanowire MOSFETs with various diameters of 120, 75, and 45 nm have been fabricated. The device with a diameter of 120 nm shows threshold voltage of 0.7 V, drain saturation voltage of 0.5 V, and subthreshold swing of 70 mV/decade, which would be suitable for low voltage/power applications. However, the devices with smaller diameter of 75 and 45 nm show peculiar characteristics, such as a second rise of the drain current in output characteristics and a negative transconductance. Systematical analyses with dc and noise measurements as well as TCAD simulations show that the observed characteristics are due to the contact potential which strongly depends on the nanowire diameter and the trapping effect into deep traps at the sidewall surface of the nanowire channel. Index Terms--GaN vertical nanowire MOSFET, low voltage application, nanowire diameter, contact potential, negative transconductance I. INTRODUCTION -V semiconductors such as GaAs and InAs offer superior material and electrical properties and are considered to replace the channel layers in the conventional Si-based devices which technologies have been quiet close to their limitations [1-6]. In contrast with other III-V

A Simulation Study on the Effects of Interface Charges and Geometry on Vertical GAA GaN Nanowire MOSFET for Low-Power Application

“…The channel and the source/drain access regions were doped with 5 × 10 17 cm −3 and 2 × 10 18 cm −3 , respectively. The dimensions of the MOSFETs considered in this work are based on the experimentally obtained devices [19] already fitted to simulation in [18], scaled down considering experimentally obtainable dimensions based on the present technology for GaN material.…”

Design and analysis of asymmetrical low-k source side spacer halo doped nanowire metal oxide semiconductor field effect transistor

“…The increased gate control over the channel and immunity to short channel effects are of supreme importance to scaling the device in nanometer regions without disturbing the performance of the device [5]. However, multi-gate technology has shown ways of improving these characteristics [6]- [9]. The construction of MOSFETs by using nanowires with a gate-all-around configuration promises scalability to any length due to increased immunity to short-channel effects [10]- [14] as compared to others.…”