Effects of Copper Contamination in Silicon on Thin Oxide Breakdown

Abstract

Effects of copper contamination on the breakdown and reliability characteristics of thin silicon gate oxides are discussed. Gate oxide integrity is measured for thermal oxides of 45, 75, 120, and 200 Å grown on silicon wafers intentionally contaminated with 1010–1015 cm−3 of copper. Copper doping of silicon was performed according to solubility data considerations. The oxide breakdown voltages as a function of copper concentration for the various oxide thicknesses are reported. For 45 Å oxide, copper concentration cannot exceed 1013 cm−3 without severe degradation in oxide quality. The threshold contamination level for 75 Å oxides is ten times higher. Premature oxide breakdown is proposed to occur due to copper silicide precipitation, which locally enhances the electrical field. It is concluded that the impact of copper contamination on oxide breakdown is not as severe as that of iron contamination on oxide breakdown. This is due to the difference in segregation properties of the two metals at the normalSi/SiO2 interface. © 1999 The Electrochemical Society. All rights reserved.

Impact of the Unique Physical Properties of Copper in Silicon on Characterization of Copper Diffusion Barriers

“…However, the actual critical copper concentrations vary greatly from report to report. For example, Ramappa and Henley [64] grew oxides on copper-contaminated samples and reported that the critical copper concentration, which would cause a decrease in the oxide breakdown electric field from 12 to 10 MV/cm was about 10 13 cm ± ±3 for a 4.5 nm oxides and about 10 14 cm ± ±3 of Cu for a 7.5 nm thick oxides. These concentrations correspond to the equilibrium solubility of copper at the temperatures of approximately 425 and 500 C, respectively.…”

Application Of The SPV-based Surface Lifetime Technique To In-Line Monitoring Of Surface Cu Contamination

“…The thermal constraints imposed in the back-end processing render methods sensitive to Cu in bulk Si, such as Surface PhotoVoltage (SPV) diffusion length [1], photoconductive decay [6], and SPV decay [7], as not applicable. Consequently, only methods that are able to detect Cu on the surface of Silicon are relevant.…”

“…Implementation of Cu interconnects into Silicon Integrated Circuits (IC's) has been instrumental in the continuing improvement of IC device performance. Copper as a well known Gate Oxide Integrity (GOI) killer [1,2] requires extensive protocols to minimize the possibility of cross contamination. Despite such protocols the risk for cross contamination exists, and consequently there is the need for in-line Cu cross-contamination detection metrology.…”

Oxide Wearout, Breakdown, and Reliability

“…Breakdown is initiated in the vicinity of defects in the oxide, whether these defects are intrinsic or extrinsic. Thus, breakdown can also be triggered either by impurities in the oxide [267][268][269][270][271][272][273][274][275] or by imperfections or impurities in the substrate silicon [276][277][278][279][280][281][282][283][284][285]. The breakdown patterns observed in oxides due to structural defects in the substrate are similar to the defect patterns observed in silicon vidicons due to defects in the substrates [286].…”