Effects of Dimensional Variations on Short Channel Parameters in 14 nm Channel Length TG–SOI FinFETs

Saha, Priyanka; Nanda, Swagat; Yugender, Potaraju; Dhar, Rudra Sankar

doi:10.1007/978-981-19-2004-2_4

Cited by 5 publications

(4 citation statements)

References 9 publications

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“…Another benefit is that all the s-Si regions are equated to have equal heights and widths so that H FIN becomes equal to W FIN , resulting in an aspect ratio of unity. Previously, Saha et al [24], analysed the unity aspect ratio to indebt healthier performance in comparison to other variations for SOI n-channel FinFETs. This makes the novel QW-FinFET developed here to be a 3D square device resulting in probable optimally enriched performance.…”

Section: Device Structure and Analytical Modellingmentioning

confidence: 99%

Evolution and performance analysis of quantum well FinFET for 3 nm technology node with type-II strained tri-layered hetero-channel system

Nanda,

Dhar

2024

Phys. Scr.

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3D FinFETs are meticulously scaled down to sub-14 nm leading to reemerging undesirable characteristics namely increased Drain Induced Barrier Leakage (DIBL), higher subthreshold swing and excessive leakage currents. This inhibits the scaling of FinFETs and research suggests probable utilization of strained silicon technology in FinFETs to improve the on currents and transconductance of the nano devices. The emergence of quantum effects including velocity overshoot and carrier confinement severely affects the electrical characteristics at sub-10 nm channel length devices. Therefore, amalgamation of strained silicon prove to be a boon in FinFETs while being at par with the proposed 3 nm technology node of IRDS 2018, and designing to develop reliable devices at 08 nm gate length is the requisite. Thus, exploring the design and performance investigation of novel 08 nm Quantum Well FinFETs (QW-FinFETs) incorporating a tri-layered strained silicon Heterostructure-On-Insulator (HOI)are proposed with distinct channel dimensions which are analyzed and compared with existing devices. The optimum QW-FinFET device developed for 3 nm technology node of IRDS 2018 achieved a ~25% enhancement in drain currents with Device D2 portraying almost ~103% escalations in electron mobility on account of ballistic transport of charge carriers without scattering and enriching the performance for the future generation of device resulting in faster switching operation in sub-nano regime.

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Section: Device Structure and Analytical Modellingmentioning

confidence: 99%

Evolution and performance analysis of quantum well FinFET for 3 nm technology node with type-II strained tri-layered hetero-channel system

Nanda,

Dhar

2024

Phys. Scr.

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“…The basic device structure is based on the 10 nm HOI FinFET developed by Nanda et al [20] considering a combined substrate and buried oxide height of 80 nm. The width and height of the initial device is kept at 6 nm considering the advantages of a square device depicted by Saha et al [21], and is designated device D 0 . This device D 0 and subsequently all other devices implement a tri-layered channel structure consisting of two strained silicon layers of 1.5 nm each embedding a 3 nm layer of Si 1-x Ge x in between.…”

Section: Device Structure and Theorymentioning

confidence: 99%

“…With the gate length reduced to 10 nm, the lengths of the source as well as the drain are retained at 10 nm. The height/width of the source/channel/drain are all maintained to develop square devices and optimize the devices as per Saha et al [21]. Because of Type-II band heterogeneity in s-Si and s-SiGe layer, conduction band breaks into two fold and four fold valleys evolving in decrement of effective mass [23,24].…”

Section: Device Structure and Theorymentioning

confidence: 99%

Exploration of effects of gate underlap in HOI FinFETs at 10 nm gate length

Datta,

Nanda,

Sankar Dhar

2023

Phys. Scr.

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With sub-22 nm technology nodes, the short channel effects (SCEs) arose in FinFETs, which hindered the further scaling of devices. The leakage currents became detrimental with scaling of the gate oxide thickness below 2 nm, hence the demand for control of leakage currents due to corner effects in the sidewalls of FinFETs. Research suggested use of gate underlap (GUL) architectures to suppress the leakage currents. The objective of this paper is to utilize a GUL structure in a 10 nm gate length Heterostructure-On-Insulator (HOI) FinFET, encompassing a three layered strained channel architecture to enrich the drive currents. Different structures with GUL lengths of 1 nm, 3 nm and 5 nm are designed to study the electrical characteristics besides the effects of leakage currents and other SCEs. A noteworthy decrease is observed in the leakage currents with increasing GUL lengths. However, it also leads to decrease of drive currents of the devices. A trade-off between the enhanced dimensions of source/drain along with an optimized GUL length proves beneficial in the strained silicon channel devices. The 10 nm HOI device employing a 3 nm GUL with height/width of source/drain at 8 nm provides drive currents and leakage currents at par with the 10 nm HOI device with no underlap. But with higher Ion/Ioff current ratio and lower SCEs, this device with 3 nm underlap decreases corner effects and is observed from the electron velocity and total current density contours leading to faster switching speeds and optimized device performance towards semiconductor industry.

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“…However, these are prone to increasing fringing capacitance and series resistance, which hinders the electrical performances of the devices. Saha et al [ 25 ] investigated the effects of different aspect ratios on electrical characteristics and concluded that square devices having equal heights and widths, with an aspect ratio of unity, have superior results. Table 3 therefore presents the optimised novel 10 nm three-fin Q-FinFET as Device A 1 and the novel 8 nm optimised three-fin Q-FinFET as device A 8 , while the existing 10 nm HOI TG FinFET of Nanda et al [ 24 ] for calibration and validation is termed Device A 9 .…”

Section: Device Structure and Theorymentioning

confidence: 99%

Development and Analysis of a Three-Fin Trigate Q-FinFET for a 3 nm Technology Node with a Strained-Silicon Channel System

et al. 2023

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Multi-gate field effect transistors (FETs) such as FinFETs are severely affected by short-channel effects (SCEs) below 14 nm technology nodes, with even taller fins incurring fringing capacitances. This leads to performance degradation of the devices, which inhibits further scaling of nanoFETs, deterring the progress of semiconductor industries. Therefore, research has not kept pace with the technological requirements of the International Roadmap for Devices and Systems (IRDS). Thus, the development of newer devices with superior performances in terms of higher ON currents, acceptable leakage currents and improved SCEs is needed to enable the continuance of integrated circuit (IC) technologies. The literature has advocated integration of strained-silicon technology in existing FinFETs, which is highly effective in enhancing ON currents through the strain effect. However, the ON currents can also be amplified by intensifying the number of fins in trigate (TG) FinFETs. Thus, three-fin TG quantum (Q)-FinFETs, using a novel tri-layered strained-silicon channel, are deployed here at 10 nm and 8 nm channel lengths. Threshold voltage is calculated analytically to validate the designs. The electrical parameters and quantum effects of both devices are explored, analysed and compared with respect to existing heterostructure-on-insulator (HOI) FinFETs and the proposed existing standard requirement of IRDS 2022 for a 3 nm technology node. The comparisons demonstrated a significant increase in the drive currents upon employing three fins of the same dimensions (8 nm gate length) and specifications in a device-based system. The performance is augmented in contrast to the 3 nm technology node device of IRDS 2022, with SCEs within the limits. Thus, employing a tri-layered strained-silicon channel system in each fin allowed for forming a three-fin Q-FinFET that, in our opinion, is the technique for consolidating the performance of the devices and enabling future generation device for faster switching operation in a sub-nano regime.

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Effects of Dimensional Variations on Short Channel Parameters in 14 nm Channel Length TG–SOI FinFETs

Cited by 5 publications

References 9 publications

Evolution and performance analysis of quantum well FinFET for 3 nm technology node with type-II strained tri-layered hetero-channel system

Evolution and performance analysis of quantum well FinFET for 3 nm technology node with type-II strained tri-layered hetero-channel system

Exploration of effects of gate underlap in HOI FinFETs at 10 nm gate length

Development and Analysis of a Three-Fin Trigate Q-FinFET for a 3 nm Technology Node with a Strained-Silicon Channel System

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