Effects of Excimer Laser Dopant Activation on Low Temperature Polysilicon Thin-Film Transistors with Lightly Doped Drains

Abstract

Excimer laser annealing has been utilized to manufacture low temperature polycrystalline silicon thin-film transistors with lightly doped drain ͑LDD͒ structures. The excimer laser annealing can effectively reduce the thermal budget of source/drain dopant activation, namely, without substrate heating. With the advantages of LDD structure, high performance device characteristics with a low ''off'' state current of 4.38 ϫ 10 Ϫ12 A/m, high on/off current ratio of 1.6 ϫ 10 7 , and good field-effect mobility of 268 cm 2 /V s, can be achieved simultaneously.One of the important device evaluation factors for lowtemperature poly-Si thin-film transistors ͑LTPS TFTs͒ is the current leakage. 1 The leakage current of poly-Si TFTs is correlated with current conduction through the defects at the grain boundaries and gate oxide/poly-Si interface at the high drain electric field. Therefore, lateral electric field reduction of drain junction is important to reduce the leakage current in LTPS TFTs. Although drain engineering using offset-gate structure TFTs, 2 lightly doped drain ͑LDD͒ TFTs, 3 and field-induced-drain ͑FID͒ TFTs 4 have been reported to reduce off-state leakage current, and these investigations employed conventional furnace to activate implanted dopants with high thermal budget which is too high for advanced plastic substrate. In contrast, excimer laser annealing ͑ELA͒ recently has attracted much attention because of the advantages of low process temperature even at room temperature process. Thus, ELA process has high potential for high resolution display on glass or even plastic substrate applications. 5 In this paper, ELA is therefore proposed to fabricate the LTPS TFTs with LDD structures. We have utilized a KrF excimer laser to crystallize amorphous Si and activate the dopants in the source/drain ͑s/d͒ and LDD regions of the TFTs. High field-effect mobility, low leakage current, and high on/off current ratio can be attained simultaneously. Figure 1 shows the main process sequences of the LDD poly-Si TFTs and the process steps are described as follows. 1000 Å thick amorphous silicon was first deposited by low pressure chemical vapor deposition ͑LPCVD͒ at 550°C on a Si substrate with 0.5 m thick thermal oxide. This is the highest thermal cycle used in this work and can be reduced using plasma enhanced CVD ͑PECVD͒. A scanning-type KrF excimer laser with Gaussian beam shape of 1.8 mm width and 23 mm length was used to crystallize the amorphous Si film. The condition of excimer laser crystallization is set at the energy density of 320 mJ/cm 2 and 99% overlapping of the beam width as well as 10 Hz repetition rate at 400°C substrate temperature. This crystallization resulted in the poly-Si film with an average grain size of 8000 Å. After the definition of active islands, 1000 Å thick Si dioxide film was deposited by PECVD at 300°C and used as the gate dielectric. Then 5000 Å thick Al film was thermally evaporated and used as the gate metal. The Al and the gate oxide films were patterned sequentially as the gate electrod...

Back-End Deposited Silicon Photonics for Monolithic Integration on CMOS

“…Traditional process uses furnace annealing or rapid thermal anneal to provide the necessary activation energy, but they are very high thermal budget processes, incompatible with BEOL. Instead, ELA can be used to activate dopant as demonstrated in [27], as well as forming of silicide [28] with low thermal budget.…”

Blue Laser Diode Annealed Top-Gate Low Temperature Poly-Si TFTs With Low Resistance of Source/Drain From Deposited n + Layer

“…The high Vd-dependent Ioff of LTPS TFTs is normally ascribed to the drain filed-induced carrier generation at the grain boundaries within the drain depletion region. Such Ioff strongly depends on the maximum electric field at the drain regions [26] and thus can be effectively relieved using the lightly doped drain (LDD) structure [26][27][28]. To emulate the LDD effect, a simple offset region of intrinsic poly-Si was designed between n + -drain and gate-controlled channel, as shown in Fig.…”

Low‐Temperature Polysilicon Oxide Thin‐Film Transistors with Coplanar Structure Using Six Photomask Steps Demonstrating High Inverter Gain of 264 V V−1

“…The Excimer laser annealing or continuous wave (CW) laser exposure is conducted for the activation of dopants in LTPS. [29][30][31] Note that thermal activation of the doped region in LTPS should be done at least 450 C. The laser absorption in LTPS increases its temperature for the dopant activation. The a-IGZO cannot absorb blue laser (445 nm, photon energy of 2.78 eV) due to its higher bandgap (>3 eV).…”

“…The a‐IGZO is deposited by reactive sputtering using a polycrystalline IGZO target (In 2 O 3 :Ga 2 O 3 :ZnO = 1:1:1 mol%). The Excimer laser annealing or continuous wave (CW) laser exposure is conducted for the activation of dopants in LTPS . Note that thermal activation of the doped region in LTPS should be done at least 450 °C.…”