Crystalline Au dendrites were formed by electrodeposition on a glassy carbon electrode from a solution of HAuCl(4) containing cysteine. The Au dendrites possessed a hierarchical architecture with three-fold symmetry; they comprised trunks, branches, and nanorod leaves, which all grew along the <111> direction.

4-Alkylaryl layers were electrodeposited on Au surface via formation in situ of diazonium cations and the subsequent electroreduction in solution of 4-alkylanilines (4-CH 3 (CH 2 ) n C 6 H 4 NH 2 , n = 5−13). The electrodeposited layers were characterized with X-ray photoelectron spectra (XPS), an atomic force microscope (AFM), attenuated-total-reflection infrared spectra (ATR-IR), spectroscopic ellipsometry, and water contact angle. The thickness of the deposited alkylaryl layer increased with the length of the alkyl chain, which was about 1.6 times the molecular length of the alkylaniline precursor. The surfaces of deposited adlayers were uniform and smooth without aggregation and exhibited hydrophobic character with a water contact angle ∼95°. Charge transport across the alkylaryl layer was characterized with a measurement of a conductive AFM. The current−voltage characteristics at low voltages are describable with a nonresonant tunneling mechanism, according to which the resistance increased exponentially with the thickness of the adlayer. As a measure of the efficiency of the charge transport, the average attenuation factor (β) was 0.63 Å −1 , which was less than that observed for the alkyl SAM because of the presence of the aryl ring. The breakdown voltage of the adlayer also increased with the length of the alkyl chain. The 4-tetradocylaryl layer exhibited a resistance and breakdown voltage comparable to that observed for a 1-octadecanethiolate SAM.

Low-temperature polycrystalline silicon ͑LTPS͒ thin-film transistors ͑TFTs͒ with a periodic lateral silicon grain structure have been demonstrated to exhibit high-performance electrical characteristics via the amorphous silicon spacers above the amorphous silicon film crystallized with excimer laser. Amorphous silicon spacers allowed the bottom of the under-layered amorphous silicon film to serve as seed crystals. The periodic grain structure could be artificially controlled via the super lateral growth phenomenon during excimer laser irradiation. Consequently, such periodically large and lateral grains in the TFTs would achieve high fieldeffect-mobility of 298 cm 2 /V s, as compared with the conventional ones of 128 cm 2 /V s. In addition, the uniformity of deviceto-device could be improved due to this location-manipulated lateral silicon grains.

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Excimer laser annealing has been utilized to manufacture low temperature polycrystalline silicon thin-film transistors with lightly doped drain ͑LDD͒ structures. The excimer laser annealing can effectively reduce the thermal budget of source/drain dopant activation, namely, without substrate heating. With the advantages of LDD structure, high performance device characteristics with a low ''off'' state current of 4.38 ϫ 10 Ϫ12 A/m, high on/off current ratio of 1.6 ϫ 10 7 , and good field-effect mobility of 268 cm 2 /V s, can be achieved simultaneously.One of the important device evaluation factors for lowtemperature poly-Si thin-film transistors ͑LTPS TFTs͒ is the current leakage. 1 The leakage current of poly-Si TFTs is correlated with current conduction through the defects at the grain boundaries and gate oxide/poly-Si interface at the high drain electric field. Therefore, lateral electric field reduction of drain junction is important to reduce the leakage current in LTPS TFTs. Although drain engineering using offset-gate structure TFTs, 2 lightly doped drain ͑LDD͒ TFTs, 3 and field-induced-drain ͑FID͒ TFTs 4 have been reported to reduce off-state leakage current, and these investigations employed conventional furnace to activate implanted dopants with high thermal budget which is too high for advanced plastic substrate. In contrast, excimer laser annealing ͑ELA͒ recently has attracted much attention because of the advantages of low process temperature even at room temperature process. Thus, ELA process has high potential for high resolution display on glass or even plastic substrate applications. 5 In this paper, ELA is therefore proposed to fabricate the LTPS TFTs with LDD structures. We have utilized a KrF excimer laser to crystallize amorphous Si and activate the dopants in the source/drain ͑s/d͒ and LDD regions of the TFTs. High field-effect mobility, low leakage current, and high on/off current ratio can be attained simultaneously. Figure 1 shows the main process sequences of the LDD poly-Si TFTs and the process steps are described as follows. 1000 Å thick amorphous silicon was first deposited by low pressure chemical vapor deposition ͑LPCVD͒ at 550°C on a Si substrate with 0.5 m thick thermal oxide. This is the highest thermal cycle used in this work and can be reduced using plasma enhanced CVD ͑PECVD͒. A scanning-type KrF excimer laser with Gaussian beam shape of 1.8 mm width and 23 mm length was used to crystallize the amorphous Si film. The condition of excimer laser crystallization is set at the energy density of 320 mJ/cm 2 and 99% overlapping of the beam width as well as 10 Hz repetition rate at 400°C substrate temperature. This crystallization resulted in the poly-Si film with an average grain size of 8000 Å. After the definition of active islands, 1000 Å thick Si dioxide film was deposited by PECVD at 300°C and used as the gate dielectric. Then 5000 Å thick Al film was thermally evaporated and used as the gate metal. The Al and the gate oxide films were patterned sequentially as the gate electrod...