Effects of finite register length in digital filtering and the fast Fourier transform

Oppenheim, Alan V.; Weinstein, Clifford J.

doi:10.1109/proc.1972.8820

Cited by 272 publications

(84 citation statements)

References 45 publications

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“…Fixed-point conversion and word length optimization has a long history of research dating back to [1] and [4]. In a fixed-point representation, there are basically two considerations in determining a word length, the number of integer bits and the number of fractional bits.…”

Section: Related Workmentioning

confidence: 99%

Fine Grain Precision Scaling for Datapath Approximations in Digital Signal Processing Systems

Lee

Gerstlauer

2015

IFIP Advances in Information and Communication Technology

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Section: Related Workmentioning

confidence: 99%

Fine Grain Precision Scaling for Datapath Approximations in Digital Signal Processing Systems

Lee

Gerstlauer

2015

IFIP Advances in Information and Communication Technology

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“…This analysis is later extended by the same authors to the FFT decimation-in-time algorithm [21]. Oppenheim and Weinstein [26] discussed in some detail the effects of finite register length on implementations of digital filters, and FFT algorithms.…”

Section: Related Workmentioning

confidence: 99%

A Methodology for the Formal Verification of FFT Algorithms in HOL

Akbarpour

Tahar

2004

Formal Methods in Computer-Aided Design

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Abstract. This paper addresses the formal specification and verification of fast Fourier transform (FFT) algorithms at different abstraction levels based on the HOL theorem prover. We make use of existing theories in HOL on real and complex numbers, IEEE standard floating-point, and fixed-point arithmetics to model the FFT algorithms. Then, we derive, by proving theorems in HOL, expressions for the accumulation of roundoff error in floating-and fixed-point FFT designs with respect to the corresponding ideal real and complex numbers specification. The HOL formalization and proofs are found to be in good agreement with the theoretical paper-and-pencil counterparts. Finally, we use a classical hierarchical proof approach in HOL to prove that the FFT implementations at the register transfer level (RTL) implies the corresponding high level fixed-point algorithmic specification.

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“…using fixed-point arithmetic shows that the fixedpoint FFT can save at least 35% memory resource. The challenge of using fixedpoint is how to handle the quantization error [9]. We carry out a group of fixedpoint simulation to determine the internal wordlength of our design.…”

Section: Introductionmentioning

confidence: 99%

A high-precision hardware-efficient radix-2<sup>k</sup> FFT processor for SAR imaging system

Yang

Xie

Chen

et al. 2016

IEICE Electron. Express

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This paper presents a high-precision, hardware-efficient FFT processor for an on-board SAR (synthetic aperture radar) imaging system. To meet the high resolution imaging and big data granularity processing requirements, a radix-2 k mixed FFT algorithm is proposed. The mixed radix FFT algorithm reduces the number of complex multiplication and the size of twiddle factor memory. To further reduce hardware resource and improve FFT precision, sufficient fixed-point simulation is performed for the fixedpoint FFT processor design. As a proof of concept, a 32768-point fixed-point processor is implemented on XC6VCX240T FPGA platform. The proposed pipelined FFT processor achieves a signal-to-quantization noise ratio (SQNR) of 47.3 dB at 18-bit internal wordlength. Compared with Xilinx FFT v7.1 IP core, the results demonstrate that our design saves at least 11% memory and 57% arithmetic elements.

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Effects of finite register length in digital filtering and the fast Fourier transform

Cited by 272 publications

References 45 publications

Fine Grain Precision Scaling for Datapath Approximations in Digital Signal Processing Systems

Fine Grain Precision Scaling for Datapath Approximations in Digital Signal Processing Systems

A Methodology for the Formal Verification of FFT Algorithms in HOL

A high-precision hardware-efficient radix-2<sup>k</sup> FFT processor for SAR imaging system

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