Effects of gate depletion and boron penetration on matching of deep submicron CMOS transistors

Abstract

This paper presents new insights into the mechanisms of gate depletion and boron penetration in deep submicron CMOS technologies. MOSFET matching measurements show that these effects are stochastic in nature, and are associated with the gate poly-Si grain size distribution. Moreover, this work demonstrates that these effects can strongly degrade transistor matching performance of future CMOS generations.

Polysilicon gate enhancement of the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFETs with ultrathin gate oxide

“…As mentioned in the introduction, the grain structure of the polysilicon itself and particularly the effects associated with the grain boundaries introduce also mismatch in the threshold voltage of deep submicron MOSFET's [12]. The enhanced diffusion and segregation along the grain boundaries lead to a nonuniform polysilicon doping which may be complemented by a local penetration of dopants in the channel region.…”

“…For oxide thicknesses and channel doping levels typical for sub-100 nm MOSFET's, the polysilicon depletion effect starts to dominate the inversion charge losses [10], [11]. In addition to this the granularity of the polysilicon gate can be responsible for a substantial mismatch in the parameters of deep submicron CMOS transistors [12].…”

Interpretation of MOS transistor mismatch signature through statistical device simulations

“…Several experiments have been performed over the years on the impact of certain process conditions on the mismatch. A good example of these experiments is the study of the impact of metal coverage, and gate depletion with boron penetration on MOS transistor mismatch, both published by Tuinhout et al [27,28]. Many other contributions about test structures and analysis methods appear regularly at the International Conference on Microelectronics Test Structure (ICMTS) [29].…”

“…Statistical simulations represent an easy and fast way (in fact probably the only viable way) to study the effect of controlled mismatch causes in modern MOS device architectures. There are examples of very well controlled experiments (see [28] for an experiment of the impact of boron penetration on mismatch) but they are certainly very expensive and are not always successful. One may argue that the use of a compact model is a very fast and inexpensive way to see the effect of individual sources of mismatch as well.…”

“…Among them, poly-silicon granularity [28,31], line edge roughness [67,15] and fixed oxide charges [52] are the ones that recently attracted the most attention.…”