“…The same simulation was also performed on GaAs FinFET, and similarly, La 2 O 3 was capable of achieving the smallest DIBL (47 mV/V), lowest SS (76 mV/dec), and highest g m among all the gate dielectrics [149]. As for TG FinFET, simulation was carried out on SOI substrate by the SILVACO TCAD simulator with the device structure depicted in Figure 17d [150]. The L g , EOT, fin width and height, buried-oxide thickness, body, and source/drain doping concentrations are set as 30, 1.2, 10, 20 nm, 5 × 10 17 cm −3 , and 5 × 10 20 cm −3 , respectively.…”