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In this work the corner effect sensitivity to fin geometry variation in multifin dual and tri-gate SOI-FinFETs is studied through a commercial, three-dimensional numerical simulator ATLAS from Silvaco International [1]. These devices are compatible with conventional silicon integrated circuit processing, but offer superior performance as the device is scaled into the nanometer range. This study aims wider to use multiple fins between the source and drain regions. The results indicate that for both multifin double and triple gate FinFETs, the corner effect does not lead to an additional leakage current and therefore does not deteriorate the SOI-FinFET performance.

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In this paper, we present the results of a 3D-numerical simulation of SOI TRI-GATE FinFET transistor. 3D-device structure, based on technology SOI (Silicon-On-Insulator) is described and simulated by using SILVACO TCAD tools and we compare the electrical characteristics results for Titanium Nitride (TiN) fabricated on Al2O3 (k ~ 9), HfO2 (k ~ 20) and La2O3 (k ~ 30) gate dielectric. Excellent dielectric properties such as high-k constant, low leakage current, threshold voltage and electrical characteristics were demonstrated. The implementation of high-k gate dielectrics is one of several strategies developed to allow further miniaturization of microelectronic components. From the simulation result; it was shown that HfO2 is the best dielectric material with metal gate TiN, which giving better subthreshold swing (SS), drain-induced barrier lowing (DIBL), leakage current Ioff and Ion/Ioff ratio.

The objectives of this work are focused on the application of strained silicon on MOSFET transistor. To do this, impact and benefits obtained with the use of strained silicon technology on p-channel MOSFETs are presented. This research attempt to create conventional and two-strained silicon MOSFETs fabricated from the use of TCAD, which is a simulation tool from Silvaco. In our research, two-dimensional simulation of conventional MOSFET, biaxial strained PMOSFET and dual channel strained P-MOSFET has been achieved to extract their characteristics. ATHENA and ATLAS have been used to simulate the process and validate the electronic characteristics. Our results allow showing improvements obtained by comparing the three structures and their characteristics. The maximum of carrier mobility improvement is achieved with percentage of 35.29 % and 70.59 % respectively, by result an improvement in drive current with percentage of 36.54 % and 236.71 %, and reduction of leakage current with percentage of 59.45 % and 82.75 %, the threshold voltage is also enhaced with percentage of: 60 % and 61.4%. Our simulation results highlight the importance of incorporating strain technology in MOSFET transistors.