Effects of lithography non-uniformity on device electrical behavior. Simple stochastic modeling of material and process effects on device performance

Patsis, G. P.; Constantoudis, Vassilios; Gogolides, Εvangelos

doi:10.1007/s10825-006-0014-9

Cited by 3 publications

(1 citation statement)

References 16 publications

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“…The impact of process variations and non-uniformities on the performance of an electrical device is a key metric to characterize the quality and robustness of a lithographic patterning step within the manufacturing of an integrated circuit. For many years, simulation studies have been used to investigate the impact of factors such as line width roughness on device performance, and to link the results to material and process parameters [1].…”

Section: Introductionmentioning

confidence: 99%

Electrical analysis of a stochastically simulated 2 nm node electrical test structure

Melvin¹,

Demmerle

Siebert

et al. 2023

DTCO and Computational Patterning II

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Integrated circuit performance has been limited by transistor performance for many process nodes. However, in advanced nodes where pitches reach 10s of nanometers in size, there is an increasing probability of cases where circuit timing may be limited by the resistance and capacitance of the device rather than the transistor. This means that metal layer patterning may have implications on device performance beyond reliability, shorts, and opens. Lithography variation can be effectively predicted using stochastic simulations, including layer overlay. Simulating many patterns stochastically produces insight into the performance of the lithography process over time. Etching and metallizing the pattern set in simulation then allows the study to extend to electrical simulations. The combined lithography and electrical simulation data can then be used together to improve process or pattern performance before constructing a reticle. These data also allow the engineering teams to address resist and capacitance issues that may impact device performance prior to tapeout. This paper will investigate the metal layers of a structure designed to emulate an advanced node logic circuit that uses a CFET transistor. The structure will be corrected with OPC, and each layer will be simulated to generate a large (100) set of stochastic patterns at multiple process conditions in focus, overlay, and exposure. Each of these patterns will then be etched in a modeled process and metalized with copper. Finally, resistance and capacitance measurements will be generated from circuit simulations. The output data will then be used to update the lithography process or the pattern to improve through process performance including electrical characteristics.

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Section: Introductionmentioning

confidence: 99%

Electrical analysis of a stochastically simulated 2 nm node electrical test structure

Melvin¹,

Demmerle

Siebert

et al. 2023

DTCO and Computational Patterning II

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Modelling MOSFET gate length variability for future technology nodes

Patsis

2008

Physica Status Solidi (a)

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Gate length variability due to intra or inter die variations can lead to considerable mismatch between devices even inside the same chip. This variability has to be considered in detail and new device models should be developed, aiming in modelling its effects on the electrical characteristics devices. In this work the Philips MM11 MOSFET model is extended to incorporate gate length variability. This is introduced by dividing the device width into sub‐units following a Gaussian gate length distribution, with appropriate line‐width roughness. The combined model is used to quantify the drain‐source current in terms of gate line‐width roughness. The model is coded in VHDL‐AMS in order to be used for simulation of circuit behaviour inside the framework of appropriate system simulation software such as Ansfoft's Simplorer. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

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A simulation study on the impact of lithographic process variations on CMOS device performance

Fühner

Kampen

Kodrasi

et al. 2008

Optical Microlithography XXI

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In this paper, we demonstrate how a direct coupling of a lithography simulation program and a semiconductor device simulation tool can be used to investigate the impact of lithographic process variations on nano-scaled CMOS devices. In contrast to conventional evaluation criteria such as process windows, mask error enhancement factor (MEEF), or CD (critical dimension) uniformity, the lithography process is regarded in a more holistic fashion as a means to an end. As a consequence, the ultimate figure of merit is determined by the performance of the device. Lithography simulations are conducted using a rigorous EMF solver for the computation of the mask nearfield. TCAD process and device simulations are performed for an ultra thinned body fully depleted silicon on insulator (UTB FD-SOI) nMOSFET, with a physical gate length of 32 run. Electrical parameters such as on- and off-current, threshold voltage, sub-threshold slope, gate-capacitance, and contact resistances are computed and extracted. The impact of lithographic process variations on the electrical behavior of the target device is surveyed and illustrated. Moreover, we present an adjusted lithography process window defined by the electrical behavior of the device. In addition to a discussion of the obtained results, this paper also focuses on the software design aspects of interfacing a lithography simulation environment with a device simulator. The steps involved in extracting parameters and transferring them from one program to the other are explained, and further automation capabilities are suggested. Moreover, it is illustrated how this approach can be extended towards an integrated litho/device process optimization procedure

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Effects of lithography non-uniformity on device electrical behavior. Simple stochastic modeling of material and process effects on device performance

Cited by 3 publications

References 16 publications

Electrical analysis of a stochastically simulated 2 nm node electrical test structure

Electrical analysis of a stochastically simulated 2 nm node electrical test structure

Modelling MOSFET gate length variability for future technology nodes

A simulation study on the impact of lithographic process variations on CMOS device performance

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