Effects of Postetching Treatment on Molecular-Pore-Stacking/Cu Interconnects for 28 nm Node and Beyond

The developments in advanced interconnect technology for semiconductor logic devices for the mitigation of plasma‐induced damage to low‐dielectric‐constant (low‐k) materials, including fluorosilicate glass and carbon‐doped silicon oxide is reviewed. The chemical bond structures of low‐k materials are summarized to help mitigate the k value degradation caused by moisture uptake after plasma processes. Damage suppression is accomplished by integrating deposition chemistries, pattern etch transfer, and post‐etch cleaning technologies. On the basis of analyses results, a discussion on the bond engineering of low‐k materials and their degradation during plasma processing is given. Challenges facing low‐k interconnect technology are also addressed.

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Review of methods for the mitigation of plasma‐induced damage to low‐dielectric‐constant interlayer dielectrics used for semiconductor logic device interconnects

Miyajima

Ishikawa

Sekine

et al. 2019

Plasma Processes & Polymers

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Highly reliable molecular-pore-stacking (MPS)/Cu interconnects featuring best combination of post-etching treatment and resputtering processes

Oshida¹,

Kume²,

Katsuyama³

et al. 2014

Microelectronic Engineering

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Effects of Postetching Treatment on Molecular-Pore-Stacking/Cu Interconnects for 28 nm Node and Beyond

Cited by 2 publications

References 6 publications

Review of methods for the mitigation of plasma‐induced damage to low‐dielectric‐constant interlayer dielectrics used for semiconductor logic device interconnects

Review of methods for the mitigation of plasma‐induced damage to low‐dielectric‐constant interlayer dielectrics used for semiconductor logic device interconnects

Highly reliable molecular-pore-stacking (MPS)/Cu interconnects featuring best combination of post-etching treatment and resputtering processes

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