Efficacy of port and lane staggering in reducing IO power supply noise

Integrated voltage regulators with high-side NMOS power switch and dedicated bootstrap driver using vertical body channel MOSFET under 100 MHz switching frequency for compact system and efficiency enhancement

“…If C BST is relatively large for integration in a chip in the design, it should be implemented on a package like the passive elements L and C OUT , which is a standard manner in IVR. [5][6][7]…”

“…Passive components such as the inductor, decoupling capacitor, and bootstrap capacitor are assumed to be utilized on the package, which is similar to the conventional IVR. [5][6][7] The cascode bridge circuit in the proposed IVR is composed of an HS NMOS power switch (M1, M2) and an LS NMOS power switch (M3, M4). Different from the conventional IVR with planar MOSFETs, the body is not connected to the source because there is no need to vary the potential during switching operation in a vertical BC MOSFET.…”

“…To achieve a very high switching frequency such as 100 MHz, integrated voltage regulators (IVRs) implemented with lowvoltage CMOS technology have become a topic of great interest. [3][4][5][6][7][8][9][10][11][12] Recent investigations have demonstrated that a DC-DC converter using bulk CMOS technology achieved a high efficiency of more than 90% under a low switching frequency such as 1 MHz with a low conversion ratio (V O =V IN = 1.2 V=3.0 V). 13) It has also been reported that a 100 MHz 90% efficiency DC-DC converter has a conversion ratio as large as (V O =V IN = 2.4 V=3.3 V).…”

“…An IVR is integrated in state-of-the-art microprocessors for several merits. [5][6][7] One of the important specifications of the IVR is the conversion ratio defined as V OUT =V IN . Generating a lower output voltage such as 1.2 V from a higher input voltage such as 3.3 V enables us to lower the energy loss of off-chip DC-DC converters, enhances the quality of the voltage regulation, and decreases the number of I=O pads, which is especially important for the microprocessor power supply.…”

“…5,6,[9][10][11] To enhance efficiency under a high switching frequency such as 100 MHz, a cascode bridge circuit in which several MOSFETs are connected in series is widely applied for the power stage because low-voltage CMOS devices in series have lower on-resistance R on and gate charge Q g than a single high-voltage CMOS device. 3,[5][6][7][8][9][10][11] In conventional IVRs using bulk CMOS technology, the output stage is configured by two p-type and two n-type MOSFETs for high efficiency under high switching frequency, as shown in Fig. 1.…”