Efficiency Analysis for a Mixed-Signal Focal Plane Processing Architecture

Abstract

Abstract. Monolithic integration of photodetectors, analog-to-digital converters, data storage, and digital processing can improve both the performance and the efficiency of future portable image products. However, digitizing and processing a pixel at the detection site presents the design challenge to deliver a system with the required performance at the lowest cost, not just a system with the highest performance. This paper analyzes the area-time efficiency, the area efficiency, and the energy efficiency of a mixed-signal, SIMD focal plane processing architecture that executes front-end image applications with neighborhood processing. Implementations of the focal plane architecture achieve up to 81x higher area efficiency and up to 11x higher energy efficiency when compared to traditional TI DSP chips. Higher efficiency ratings are required to maintain portability while addressing technology limitations such as interconnect wiring density, heat extraction, and battery life. Systems can be implemented with a less expensive fabrication technology by increasing the number of pixels per processing element (PPE).

Asynchronous cellular logic network as a co‐processor for a general‐purpose massively parallel array

“…When implemented on a fully parallel, synchronous processor‐per‐pixel SIMD array, such algorithm requires many iterative steps ( O ( N 2 ) for N × N image) executed concurrently on all N × N processors, and therefore it has a high computational cost (and correspondingly inefficient use of hardware and high‐power consumption). In order to optimize global operations on cellular processor arrays, it is necessary to look for approaches alternative to SIMD 11–14.…”

“…However, the classical CNNs have proven to be impractical for hardware implementation. A number of processor‐per‐pixel array architectures, designed specifically for asynchronous data‐flow processing, have been presented in the literature, including the work on grey‐scale morphology 13, segmentation 14, skeletonization 18 and rank‐order filtering 19. However, the algorithm‐specific designs not only have a limited functionality, but also occupy relatively large silicon area, which is the major drawback when used as a co‐processor for a general‐purpose cellular processor array.…”