Efficient absolute difference circuits in Virtex-5 FPGAs

Efficient Absolute Difference Circuit for SAD Computation On FPGA

“…For absolute difference calculation, one method is to detect the smaller operand in the absolute difference computation |CB−RB| and to subtract it from the larger operand [4], [5].The other method comprises of complimenting the smaller of the two numbers and then performing addition of two numbers followed by plus one to compute the absolute difference [6]. To compute the absolute difference for SAD, in [7] a novel architecture is optimized for realizing efficient absolute difference circuits in Virtex-5 FPGA devices which uses the 6-input look-up tables available within the chosen devices family to maximize speed performance and to minimize the amount of occupied resources. In [8] an improved architecture for efficiently computing the sum of absolute differences (SAD) on FPGAs is proposed based on a configurable adder/subtractor implementation in which each adder input can be negated at runtime.…”

A Fabric Component Based Approach to the Architecture and Design Automation of High-Performance Integer Arithmetic Circuits on FPGA

“…2.19 to ensure compact implementation. The absolute difference circuit has been realized as was proposed in [33] which comprises of a less-than comparator (Fig. 2.20) and a subtractor ( The output of the less-than comparator A_l_B n decides upon the operation A − B or B − A.…”

“…2.20) and a subtractor ( The output of the less-than comparator A_l_B n decides upon the operation A − B or B − A. For an n-bit less than comparator, its output A_l_B n is obtained using the following Boolean logic recurrence relation: [33] The absolute difference circuit has been pipelined using the "FDCPE" Xilinx primitive [4] where these FFs are presetted if the output from the previous carry chain of the adjacent slice is high and cleared if low. An intermediate output A_l_B (which decided whether to compute A− B or B − A) of the absolute difference circuit serves as a select line to the multiplexer which outputs the minimum of two numbers.…”