“…Others implement hardware-based CEP on FPGAs at gigabit wire speed [48]. The expressive power of these approaches is limited since they do not support Kleene closure [29], nor aggregation [13,21,22,36,38,48], nor various event matching semantics [13-15, 21, 29, 33, 36, 38, 48]. In contrast, SASE and Flink support all these language constructs but they do not design any optimization techniques for event trend aggregation.…”