2014
DOI: 10.1007/s11433-014-5610-2
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Efficient and flexible memory architecture to alleviate data and context bandwidth bottlenecks of coarse-grained reconfigurable arrays

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Cited by 3 publications
(1 citation statement)
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“…Ref. [52] proposed a three-level data memory hierarchy, including the memory shared among arrays, the memory shared among PEs, and the exclusive memory in PEs, to support data reuse. The memory access conflicts and the required bandwidth of external memory are reduced, increasing the performance by 20%.…”
Section: Memory Access Efficiencymentioning
confidence: 99%
“…Ref. [52] proposed a three-level data memory hierarchy, including the memory shared among arrays, the memory shared among PEs, and the exclusive memory in PEs, to support data reuse. The memory access conflicts and the required bandwidth of external memory are reduced, increasing the performance by 20%.…”
Section: Memory Access Efficiencymentioning
confidence: 99%