Efficient and Optimized Methods for Alleviating the Impacts of IR-Drop and Fault in RRAM Based Neural Computing Systems

Huang, Chenglong; Xu, Nuo; Qiu, Keni; Zhu, Yujie; Ma, Desheng; Fang, Liang

doi:10.1109/jeds.2021.3093478

Cited by 21 publications

(13 citation statements)

References 27 publications

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“…[ 27–29 ] Third, including the IR voltage drop constraint when designing the circuit architecture, enhances its robustness to the phenomenon. [ 29–31 ]…”

Section: Resultsmentioning

confidence: 99%

1S1R Optimization for High‐Frequency Inference on Binarized Spiking Neural Networks

Lopez

Rafhay

Dampfhoffer

et al. 2022

Adv Elect Materials

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in graphics processing units (GPUs) or central processing units (CPU) remains extremely challenging. On the contrary, the brain promises very high cognitive capacity while preserving exceptional energy efficiency. One of the main differences between GPUs or CPUs and the brain is memory management. On the one hand, a physical separation exists in GPUs and CPUs between arithmetic and storage units, which is at the origin of enormous energy consumption associated with data transfer between both units. [1] This trend is particularly exacerbated for Artificial Neural Networks (ANNs), which require a very large amount of memory access. On the other hand, the biological neurons and synapses are close to each other in the brain. Accordingly, developing non-von-Neumann architectures to perform in or near-memory computing with non-volatile memory (NVM) technologies is one of the most promising strategies to improve the energetic efficiency of artificial intelligence. [2] Another relevant difference between artificial processors and the brain is the way information is coded. On the one hand, GPUs and CPUs rely on high-precision floating-point outputs. On the other hand, binarized sparse and asynchronous spikes are used to communicate in the brain. In particular, a neuron receives through Single memristor crossbar arrays are a very promising approach to reduce the power consumption of deep learning accelerators. In parallel, the emerging bio-inspired spiking neural networks (SNNs) offer very low power consumption with satisfactory performance on complex artificial intelligence tasks. In such neural networks, synaptic weights can be stored in nonvolatile memories. The latter are massively read during inference, which can lead to device failure. In this context, a 1S1R ( 1Selector 1 Resistor) device composed of a HfO 2 -based OxRAM memory stacked on a Ge-Se-Sb-N-based ovonic threshold switch (OTS) back-end selector is proposed for high-density binarized SNNs (BSNNs) synaptic weight hardware implementation. An extensive experimental statistical study combined with a novel Monte Carlo model allows to deeply analyze the OTS switching dynamics based on field-driven stochastic nucleation of conductive dots in the layer. This allows quantifying the occurrence frequency of OTS erratic switching as a function of the applied voltages and 1S1R reading frequency. The associated 1S1R reading error rate is calculated. Focusing on the standard machine learning MNIST image recognition task, BSNN figures of merit (footprint, electrical consumption during inference, frequency of inference, accuracy, and tolerance to errors) are optimized by engineering the network topology, training procedure, and activations sparsity.

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“…[ 27–29 ] Third, including the IR voltage drop constraint when designing the circuit architecture, enhances its robustness to the phenomenon. [ 29–31 ]…”

Section: Resultsmentioning

confidence: 99%

1S1R Optimization for High‐Frequency Inference on Binarized Spiking Neural Networks

Lopez

Rafhay

Dampfhoffer

et al. 2022

Adv Elect Materials

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show abstract

“…Therefore, the weights in DNN should be quantized as low-precision representations with the same amount of the conductance to map. In some research works [ 8 , 19 , 20 ], the weights are typically quantized in a linear manner based on the assumption that the multiple conductance levels in ReRAM devices are linearly distributed. Figure 3 shows the relationship between the conductance levels of ReRAM cells and the linear quantization weight levels in these works.…”

Section: Preliminarymentioning

confidence: 99%

“…Thus, weights trained in the software should be quantized before mapping to the discrete conductance states. Some research works chose the linear weights’ criterion to quantize the weights based on the assumption that the conductance states provided by the ReRAM device are linear in distribution [ 8 , 19 , 20 ]. However, the actual experimental results on multi-valued ReRAM demonstrate that the distribution of the conductance values are non-linear [ 21 , 22 ].…”

Section: Introductionmentioning

confidence: 99%

Conductance-Aware Quantization Based on Minimum Error Substitution for Non-Linear-Conductance-State Tolerance in Neural Computing Systems

Huang

Wang

et al. 2022

Micromachines

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Emerging resistive random-access memory (ReRAM) has demonstrated great potential in the achievement of the in-memory computing paradigm to overcome the well-known “memory wall” in current von Neumann architecture. The ReRAM crossbar array (RCA) is a promising circuit structure to accelerate the vital multiplication-and-accumulation (MAC) operations in deep neural networks (DNN). However, due to the nonlinear distribution of conductance levels in ReRAM, a large deviation exists in the mapping process when the trained weights that are quantized by linear relationships are directly mapped to the nonlinear conductance values from the realistic ReRAM device. This deviation degrades the inference accuracy of the RCA-based DNN. In this paper, we propose a minimum error substitution based on a conductance-aware quantization method to eliminate the deviation in the mapping process from the weights to the actual conductance values. The method is suitable for multiple ReRAM devices with different non-linear conductance distribution and is also immune to the device variation. The simulation results on LeNet5, AlexNet and VGG16 demonstrate that this method can vastly rescue the accuracy degradation from the non-linear resistance distribution of ReRAM devices compared to the linear quantization method.

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“…The effective voltage or current applied to the cell is significantly reduced, which will decrease the sensing window. Using BL-enhancing schemes can compensate for certain voltage drops [54][55][56][57][58][59].…”

Section: Ir Drop Issuesmentioning

confidence: 99%

Sensing Circuit Design Techniques for RRAM in Advanced CMOS Technology Nodes

et al. 2021

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Resistive random access memory (RRAM) is one of the most promising new nonvolatile memories because of its excellent properties. Moreover, due to fast read speed and low work voltage, it is suitable for seldom-write frequent-read applications. However, as technology nodes shrink, RRAM faces many issues, which can significantly degrade RRAM performance. Therefore, it is necessary to optimize the sensing schemes to improve the application range of RRAM. In this paper, the issues faced by RRAM in advanced technology nodes are summarized. Then, the advantages and weaknesses in the novel design and optimization methodologies of sensing schemes are introduced in detail from three aspects, the reference schemes, sensing amplifier schemes, and bit line (BL)-enhancing schemes, according to the development of technology in especially recent years, which can be the reference for designing the sensing schemes. Moreover, the waveforms and results of each method are illustrated to make the design easy to understand. With the development of technology, the sensing schemes of RRAM become higher speed and resolution, low power consumption, and are applied at advanced technology nodes and low working voltage. Now, the most advanced nodes the RRAM applied is 14 nm node, the lowest working voltage can reach 0.32 V, and the shortest access time can be only a few nanoseconds.

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Efficient and Optimized Methods for Alleviating the Impacts of IR-Drop and Fault in RRAM Based Neural Computing Systems

Cited by 21 publications

References 27 publications

1S1R Optimization for High‐Frequency Inference on Binarized Spiking Neural Networks

1S1R Optimization for High‐Frequency Inference on Binarized Spiking Neural Networks

Conductance-Aware Quantization Based on Minimum Error Substitution for Non-Linear-Conductance-State Tolerance in Neural Computing Systems

Sensing Circuit Design Techniques for RRAM in Advanced CMOS Technology Nodes

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