Efficient and reliable fault analysis methodology for nanomagnetic circuits

Turvani, Giovanna; Riente, Fabrizio; Cairo, Fabrizio; Vacca, Marco; Garlando, Umberto; Zamboni, Maurizio; Graziano, Mariagrazia

doi:10.1002/cta.2252

Cited by 25 publications

(12 citation statements)

References 54 publications

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“…Starting from the designed structure, MagCAD allows the extraction of the VHDL description of the circuit, that is based on a compact VHDL model [35] of pNML devices. The generated VHDL can be used to simulate (using a common HDL simulator) and verify the functionality of the circuit [54,55,56]. The complexity of the pNML-based CLiM array depends on the complexity of the interconnections between CLiM cells, as it can be noticed from Section 4.4.…”

Section: Beyond Cmos: a Pnml Implementationmentioning

confidence: 99%

New Logic-In-Memory Paradigms: An Architectural and Technological Perspective

2019

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Processing systems are in continuous evolution thanks to the constant technological advancement and architectural progress. Over the years, computing systems have become more and more powerful, providing support for applications, such as Machine Learning, that require high computational power. However, the growing complexity of modern computing units and applications has had a strong impact on power consumption. In addition, the memory plays a key role on the overall power consumption of the system, especially when considering data-intensive applications. These applications, in fact, require a lot of data movement between the memory and the computing unit. The consequence is twofold: Memory accesses are expensive in terms of energy and a lot of time is wasted in accessing the memory, rather than processing, because of the performance gap that exists between memories and processing units. This gap is known as the memory wall or the von Neumann bottleneck and is due to the different rate of progress between complementary metal–oxide semiconductor (CMOS) technology and memories. However, CMOS scaling is also reaching a limit where it would not be possible to make further progress. This work addresses all these problems from an architectural and technological point of view by: (1) Proposing a novel Configurable Logic-in-Memory Architecture that exploits the in-memory computing paradigm to reduce the memory wall problem while also providing high performance thanks to its flexibility and parallelism; (2) exploring a non-CMOS technology as possible candidate technology for the Logic-in-Memory paradigm.

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Section: Beyond Cmos: a Pnml Implementationmentioning

confidence: 99%

New Logic-In-Memory Paradigms: An Architectural and Technological Perspective

2019

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“…Up to now, extensive attempts has been made on the design of various digital circuits such as multipliers, adders, multiplexers, and memories in QCA technology, but according to a study in Bahar et al, the high complexity of nanocircuit structures results in the need to design high fault‐tolerant structures. QCA technology encounters challenges like many defects that were first described in previous works . Other defects, such as additional cell, cell omission defects, and the cell displacement (cell misalignment), can be found in the QCA logic, which latter is characterized as one of the main defects and faults in the QCA.…”

Section: Introductionmentioning

confidence: 99%

Robust QCA full‐adders using an efficient fault‐tolerant five‐input majority gate

Ahmadpour

Mosleh

Heikalabad

2019

Circuit Theory & Apps

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Quantum-dot cellular automata (QCA) is considered as a top candidate for nanoscale technologies with unique features such as very low occupancy and ultralow power consumption. Despite the potential benefits of QCA technology over CMOS technology, QCA circuits are highly prone to defects. Therefore, a demand has risen in designing fault-tolerant circuits. In this research, a novel fault-tolerant five-input majority gate is first suggested, and then it is evaluated by implementing a variety of faults such as cell omission, cell displacement, and extra-cell deposition. The evaluation results reveal that the proposed structure is 100%, 51.85%, and 18.8% fault-tolerant under extra-cell deposition, single-cell omission, and double-cell omission, respectively. Moreover, two single-layer and coplanar fault-tolerant QCA full-adders are offered using the suggested fault-tolerant structure. The stability of the presented single-layer full-adder has also been investigated under single and double cell omission defects. The evaluation outcomes show that the suggested fault-tolerant single-layer full-adder has a high stability in Sum and C out outputs compared with other full-adders. In order to validate the functionality of the suggested fault-tolerant five-input majority gate, a number of physical investigations are given. The QCADesigner 2.0.3 software has been used to evaluate the simulation results.KEYWORDS five-input majority gate, circuit design, fault-tolerant, full-adders, nanotechnology, quantum-dot cellular automata (QCA)

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“…In fabricated circuits, process variations and thermal noise cause errors in the propagation of the information in long chains of nanodevices: the magnetic field generated by each cell is not sufficient to properly switch other devices without external help [3,4]. This proves the need for a clocking mechanism.…”

Section: Introductionmentioning

confidence: 99%

Physical Simulations of High Speed and Low Power NanoMagnet Logic Circuits

Turvani

D’Alessandro

Vacca

2018

JLPEA

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Among all “beyond CMOS” solutions currently under investigation, nanomagnetic logic (NML) technology is considered to be one of the most promising. In this technology, nanoscale magnets are rectangularly shaped and are characterized by the intrinsic capability of enabling logic and memory functions in the same device. The design of logic architectures is accomplished by the use of a clocking mechanism that is needed to properly propagate information. Previous works demonstrated that the magneto-elastic effect can be exploited to implement the clocking mechanism by altering the magnetization of magnets. With this paper, we present a novel clocking mechanism enabling the independent control of each single nanodevice exploiting the magneto-elastic effect and enabling high-speed NML circuits. We prove the effectiveness of this approach by performing several micromagnetic simulations. We characterized a chain of nanomagnets in different conditions (e.g., different distance among cells, different electrical fields, and different magnet geometries). This solution improves NML, the reliability of circuits, the fabrication process, and the operating frequency of circuits while keeping the energy consumption at an extremely low level.

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Efficient and reliable fault analysis methodology for nanomagnetic circuits

Cited by 25 publications

References 54 publications

New Logic-In-Memory Paradigms: An Architectural and Technological Perspective

New Logic-In-Memory Paradigms: An Architectural and Technological Perspective

Robust QCA full‐adders using an efficient fault‐tolerant five‐input majority gate

Physical Simulations of High Speed and Low Power NanoMagnet Logic Circuits

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