Efficient application of modern logic synthesis in FPGA-based designing of information and signal processing systems

Optimization based on the minimum maximal k-partial-matching problem of finite states machines with input multiplexing

“…Constraints ( 15) and ( 16) ensure the coherence of z e,i and y x,i . Constraint (15) guarantees that an edge e ≡ (r , x) belongs to P i only if the input x ∈ X (P i ) (i.e., z e,i is equal to 1 only if y x,i = 1), and ( 16) imposes that an input x belongs to X (P i ) only if there exists at least one edge e ≡ (r , x) ∈ P i . Regarding the number of selection bits, (17) ensures that d j,i = 0 for all j such that 2 j > |X (P i )| − 1; (18), that d k,i = 1 for the greatest k such that 2 k ≤ |X (P i )| − 1; and (19), that d j,i = 1 for all j < k. As a result, given i, the number of d j,i variables whose value is 1 is equal to the number of bits required for the binary representation of…”

“…In recent years, different techniques to reduce the number of required EMBs by using a small number of LUTs have been proposed [4,9,11,[13][14][15]. The EMB-based FSM implementations generated by these techniques make a more efficient use of the available FPGA resources, allowing an adequate trade-off between EMB and LUT usage.…”

“…The EMB-based FSM implementations generated by these techniques make a more efficient use of the available FPGA resources, allowing an adequate trade-off between EMB and LUT usage. Most of these techniques use functional decomposition methods to decompose the transition function of the FSM into two subfunctions: one subfunction is implemented using a combinational element (called address modifier) whereas the other is implemented using a smaller memory component [4,9,15]. Other techniques apply structural decomposition methods to divide the logic block that represents the FSM into two or more subblocks [11,16].…”