Efficient architecture mapping of FFT/IFFT for cognitive radio networks

Barahimi

Lecture Notes in Computer Science

2016

Cognitive Radios (CR) are viewed as a solution for spectrum utilization and management in next generation wireless networks. In order to adapt themselves to the actual communications environment, CR devices require highly flexible baseband processing engines. One of the most relevant operations involved in radio baseband processing is the FFT. This work presents a reconfigurable FFT processor supporting FFT sizes and throughputs required by the most used wireless communication standards. By employing Dynamic Partial Reconfiguration (DPR), the implemented design can adapt the FFT size at run-time and specialize its operation to the immediate communication demands. This translates to hardware savings, enhanced resource usage efficiency and possible power savings. The results obtained for reconfiguration times suggest that DPR techniques are a viable option for designing flexible and adaptable baseband processing components for CR devices.

Section: Related Workmentioning

confidence: 99%

Reconfigurable FPGA-Based FFT Processor for Cognitive Radio Applications

Barahimi

Lecture Notes in Computer Science

2016

“…The FFT reconfiguration is based on multiplexing modules for different sizes, so little hardware is reused. Wang et al [10] propose a run-time reconfigurable FFT/IFFT architecture for 3GPP-LTE/LTE Advanced systems, by employing a mixed-radix SDF architecture to support non-powers-of-two FFT sizes. Like in [9], DPR is not explored and the runtime reconfiguration is implemented through bypass structures which connect the pipeline elements necessary for computing an FFT with the desired size.…”

Section: Related Workmentioning

confidence: 99%

Dynamically reconfigurable FFT processor for flexible OFDM baseband processing

Barahimi

2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)

2016

The Physical layer architectures for the next generation of wireless devices will be characterized by a high degree of flexibility for real-time adaptation to communication conditions variability. OFDM-based architectures are strong candidates for the Physical layer implementation in 5G systems and one of the most important baseband processing operations required by this waveform is the Fast Fourier Transform (FFT). This paper proposes a dynamically reconfigurable FFT processor supporting FFT sizes and throughputs required by the most widely used wireless standards. The FFT reconfiguration was achieved by means of FPGA-based Dynamic Partial Reconfiguration (DPR) techniques, which enables run-time FFT size adaptation according to communication requirements and better resource utilization. The impact of DPR in terms of reconfiguration time and power consumption overhead was evaluated. The obtained results encourage the exploitation of DPR techniques to implement reconfigurable hardware infrastructures for OFDM baseband processing engines.

“…It is possible to merge 2, 3, 4 and 5-point DFT structures to a unified datapath [153] which reduces total hardware cost, but it is still not directly suitable for implementation in a general processor datapath if existing hardware should be reutilized. Others have used this structure for processor-based implementations, but the target is then an FFT-specific processor [154]. For a more general datapath, there are many additional constraints.…”

Section: Non-power-of-2 Transformsmentioning

confidence: 99%

Design of Energy-Efficient High-Performance ASIP-DSP Platforms

Karlsson¹

Cover imageChip layout of an ePUMA system with 8 compute clusters, each with a local controller, 8 compute cores and 1536kB of local compute data memory. The complete chip contains 73 processor cores and occupies 45mm 2 in 28nm FDSOI technology.(Parts of this thesis are reprinted with permission from the IEEE.)Printed by LiU-Tryck, Linköping University Linköping, Sweden, 2016 AbstractIn the last ten years, limited clock frequency scaling and increasing power density has shifted IC design focus towards parallelism, heterogeneity and energy efficiency. Improving energy efficiency is by no means simple and it calls for a reevaluation of old design choices in processor architecture, and perhaps more importantly, development of new programming methodologies that exploit the features of modern architectures.This thesis discusses the design of energy-efficient digital signal processors with application-specific instructions sets, so-called ASIP-DSPs, and their programming tools. Target applications for such processors include, but are not limited to, communications, multimedia, image processing, intelligent vision and radar. These applications are often implemented by a limited set of kernel algorithms, whose performance and efficiency are critical to the application's success. At the same time, the extreme non-recurring engineering cost of system-on-chip designs means that product life-time must be kept as long as possible. Neither general-purpose processors nor non-programmable ASICs can meet both the flexibility and efficiency requirements, and ASIPs may instead be the best trade-off between all the conflicting goals.Traditional superscalar-and VLIW processor design focus has been to improve the throughput of fine-grained instructions, which results in high flexibility, but also high energy consumption. SIMD architectures, on the other hand, are often restricted by inefficient data access. The result is architectures which spend more energy and/or time on supporting operations rather than actual computing. In addition to the hardware design, this thesis also discusses parallel programming flow for distributed memory architectures and ePUMA application implementation. A DSP kernel programming language and its compiler is presented. This effectively demonstrates how kernels written in a high-level language can be translated into HOF instructions for very high processing efficiency. Populärvetenskaplig sammanfattning PrefaceThis thesis includes material from the following first-author publications:• Andréas Karlsson, Joar Sohl and Dake Liu.Energy-efficient sorting with the distributed memory architecture ePUMA. In Proceedings of the International Symposium on Parallel and Dis-tributed Processing with Applications (ISPA), 2015.• Andréas Karlsson, Joar Sohl and Dake Liu. Cost-efficient Mapping of 3-and 5-point DFTs toGeneral Baseband Processors. In Proceedings of the International Conference on Digital SignalProcessing (DSP), 2015.• Andréas Karlsson, Joar Sohl and Dake Liu. Software-based QPP Interleaving forBaseband DS...