Efficient assembly for high order unstructured FEM meshes

Optimising Sparse Matrix Vector multiplication for large scale FEM problems on FPGA

“…We start from an efficient, parametric and customisable baseline implementation which facilitates design space exploration. By applying domain-specific customisation and instance specific design [6] we achieve a substantial improvement of resource efficiency compared to state of the art implementations [19]. In the case of our FEM case study, this increases the maximum supported problem size beyond what was previously possible on commercially available FPGAs.…”

“…In practice, larger values of P are used for large scale case studies (typically 4-7), which as explained would make our approach even more resource efficient, due to the large block sizes. However for this section we use P = 3 to provide a comparison with prior work [19], [23]. We study both the computational efficiency and the resource efficiency of the proposed design.…”

“…Applying this model and all proposed optimisations substantially reduces the resource usage for the MVMU, as shown in Section VI, enabling us to fit larger meshes than previously possible [19].…”

“…The two are connected via Infiniband through a Mellanox FDR Infiniband switch. We illustrate the benefits of the optimisations and design method proposed in Section III by providing a study of customisation opportunities on the NACA 1L FEM mesh [22] which has been used as a benchmark in previous work [19], [23]. The NACA 1L mesh is an unstructured mesh with 58728 tetrahedral elements of block size 20x20 and 11549 prismatic elements of block size 38x38 (at polynomial order P = 3).…”

“…Recently, compression techniques have been proposed to improve the performance on memory bound matrices [8], [17] The constant sparsity structure in the context of iterative methods has also been exploited to optimise FPGA architectures for SpMV [18]. Static one-off pre-processing techniques are cost-effective for FPGA implementations if they can lead either to a simplified architecture [5], [7], [19] or reduced communication overhead [8], [17]. Linear or log-linear preprocessing techniques with good performance in practice, such as the method used in this work for extracting matrix properties, have been found to be effective.…”