Efficient BISR Techniques for Word-Oriented Embedded Memories with Hierarchical Redundancy

Lu, Shyue-Kung; Yang, Chunlin; Lin, Han-Wen

doi:10.1109/icis-comsar.2006.32

Cited by 11 publications

(1 citation statement)

References 9 publications

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“…Wu brought forward using spare words to repair faulty ones, the repair rate of which is very high [6]. And a method using spare word, spare rows and columns together is proposed in [7].…”

Section: Introductionmentioning

confidence: 99%

A Self-Repairable Microprocessor

Xie¹,

Fu²,

He³

et al. 2009

ECS Trans.

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With increasing defect density, microprocessors, especially the embedded caches, will encounter more faults. Adding spare resources to replace defective components is a widely accepted method for yield enhancement. In this work, a repair method using content addressable memory combined with spare bits, as well as a novel fault injection method is proposed. With the proposed fault injection technique, various numbers and types of faults can be flexibly injected into the silicon. A wireless sensor network system using our self-repairable microprocessor (SRP) is developed to prove the effectiveness of the proposed technique.

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“…Wu brought forward using spare words to repair faulty ones, the repair rate of which is very high [6]. And a method using spare word, spare rows and columns together is proposed in [7].…”

Section: Introductionmentioning

confidence: 99%

A Self-Repairable Microprocessor

Xie¹,

Fu²,

He³

et al. 2009

ECS Trans.

View full text Add to dashboard Cite

show abstract

A software framework for dynamic self-repair in embedded SoCs exploiting reconfigurable devices

Miele¹

2010

2010 IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR)

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The realization of embedded systems for safety critical applications as Custom embedded SoCs (System on Chip) realized on FPGAs (Field Programmable Gate Array) and hybrid SoCs including both custom ASIC cores, and programmable FPGA is nowadays rapidly increasing. In recent years, fault tolerance solutions for such systems have been developed and today are still addressed by ongoing research. More recently the application of FPGA partial dynamic reconfiguration capabilities to systems fault tolerance has been investigated and demonstrated by many fresh works, but primarily from an hardware perspective. In this paper a software framework for managing dynamic partial reconfiguration is proposed. Such framework is responsible of managing the replacement of faulty hardware peripherals with soft-core versions running on reconfigurable hardware areas allowing the software applications to be unaware of the underlying fault detection and reconfiguration process.

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Design and implementation of shared BISR for RAMs: A case study

Wang

Chang

2016

2016 Ieee Autotestcon

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Efficient BISR Techniques for Word-Oriented Embedded Memories with Hierarchical Redundancy

Cited by 11 publications

References 9 publications

A Self-Repairable Microprocessor

A Self-Repairable Microprocessor

A software framework for dynamic self-repair in embedded SoCs exploiting reconfigurable devices

Design and implementation of shared BISR for RAMs: A case study

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