Efficient building block based RTL code generation from synchronous data flow graphs

Horstmannshoff, Jens; Meyr, H.

doi:10.1145/337292.337576

Cited by 9 publications

(8 citation statements)

References 6 publications

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“…Horstmannshoff et al [15], [4] developed an SDF scheduling method for complex register-transfer level building blocks. Based on timing patterns associated with token production and consumption in each actor, this method constructs a retiming graph to generate a stall signal for each SDF actor such that buffer cost is minimized.…”

Section: Related Workmentioning

confidence: 99%

“…Synchronous dataflow (SDF) [1] has been used widely as an efficient model of computation (MOC) to analyze performance and resource requirements when implementing DSP algorithms on various kinds of target architectures (e.g., see [2], [3], and [4]). The SDF model has been incorporated in many commercial tools for DSP system design, such as ADS from Agilent, LabVIEW from National Instruments, Signal Processing Designer from CoWare, and System Studio from Synopsys.…”

Section: Introductionmentioning

confidence: 99%

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Mapping Parameterized Cyclo-static Dataflow Graphs onto Configurable Hardware

Kee

Shen

Bhattacharyya

et al. 2011

J Sign Process Syst

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In recent years, parameterized dataflow has evolved as a useful framework for modeling synchronous and cyclo-static graphs in which arbitrary parameters can be changed dynamically. Parameterized dataflow has proven to have significant expressive power for managing dynamics of DSP applications in important ways. However, efficient hardware synthesis techniques for parameterized datafow representations are lacking. This paper addresses this void; specifically, the paper investigates efficient field programmable gate array (FPGA)-based implementation of parameterized cyclostatic dataflow (PCSDF) graphs. We develop a scheduling technique for throughputconstrained minimization of dataflow buffering requirements when mapping PCSDF representations of DSP applications onto FPGAs. The proposed scheduling technique is integrated with an existing formal schedule model, called the generalized schedule tree, to reduce schedule cost. To demonstrate our new, hardware-oriented PCSDF scheduling technique, we have designed a real-time base station emulator prototype based on a subset of long-term evolution (LTE), which is a key cellular standard.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Mapping Parameterized Cyclo-static Dataflow Graphs onto Configurable Hardware

Kee

Shen

Bhattacharyya

et al. 2011

J Sign Process Syst

View full text Add to dashboard Cite

show abstract

“…Synchronous dataflow (SDF) [2] has been used widely as an efficient model of computation (MOC) to analyze performance and resource requirements when implementing DSP algorithms on various kinds of target architectures (e.g., see [3,4,5]). The SDF model has been incorporated in many commercial tools for DSP system design, such as ADS from Agilent, Signal Processing Designer from CoWare, and System Studio from Synopsys.…”

Section: Introductionmentioning

confidence: 99%

FPGA-based design and implementation of the 3GPP-LTE physical layer using parameterized synchronous dataflow techniques

Kee

Bhattacharyya

Wong

et al. 2010

2010 IEEE International Conference on Acoustics, Speech and Signal Processing

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Synchronous dataflow (SDF) is an ubiquitous dataflow model of computation that has been studied extensively for efficient simulation and software synthesis of DSP applications. In recent years, parameterized SDF (PSDF) has evolved as a useful framework for modeling SDF graphs in which arbitrary parameters can be changed dynamically. However, the potential to enable efficient hardware synthesis has been treated relatively sparsely in the literature for SDF and even more so for the newer, more general PSDF model. This paper investigates efficient FPGA-based design and implementation of the physical layer for 3GPP-Long Term Evolution (LTE), a next generation cellular standard. To capture the SDF behavior of the functional core of LTE along with higher level dynamics in the standard, we use a novel PSDF-based FPGA architecture framework. We implement our PSDF-based, LTE design framework using National Instrument's LabVIEW FPGA, a recently-introduced commercial platform for reconfigurable hardware implementation. We show that our framework can effectively model the dynamics of the LTE protocol, while also providing a synthesis framework for efficient FPGA implementation.

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“…For example, [10,18,23], use a restricted form of dataflow graph called synchronous dataflow (explained in Sect. 2.1) to generate RTL.…”

Section: Introductionmentioning

confidence: 99%

Model-based mapping of reconfigurable image registration on FPGA platforms

Sen

Hemaraj

Plishker

et al. 2008

J Real-Time Image Proc

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Image registration is a computationally intensive application in the medical imaging domain that places stringent requirements on performance and memory management efficiency. This paper develops techniques for mapping rigid image registration applications onto configurable hardware under real-time performance constraints. Building on the framework of homogeneous parameterized dataflow, which provides an effective formal model of design and analysis of hardware and software for signal processing applications, we develop novel methods for representing and exploring the hardware design space when mapping image registration algorithms onto configurable hardware. Our techniques result in an efficient framework for trading off performance and configurable hardware resource usage based on the constraints of a given application. Based on trends that we have observed when applying these techniques, we also present a novel architecture that enables dynamically-reconfigurable image registration. This proposed architecture has the ability to tune its parallel processing structure adaptively based on relevant characteristics of the input images.

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Efficient building block based RTL code generation from synchronous data flow graphs

Cited by 9 publications

References 6 publications

Mapping Parameterized Cyclo-static Dataflow Graphs onto Configurable Hardware

Mapping Parameterized Cyclo-static Dataflow Graphs onto Configurable Hardware

FPGA-based design and implementation of the 3GPP-LTE physical layer using parameterized synchronous dataflow techniques

Model-based mapping of reconfigurable image registration on FPGA platforms

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