Efficient butterfly inspired optimization algorithm for analog circuits design

Lberni, Abdelaziz; Marktani, Malika Alami; Ahaitouf, Ali

doi:10.1016/j.mejo.2021.105078

Cited by 17 publications

(4 citation statements)

References 35 publications

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“…After the initialization of the population, each individual is mutated and then a new solution v ij is generated from three randomly selected parents, as given in (5). Thereafter, the crossover operation is executed to create a new solution considered as a trial solution, as described in (6). This crossover operation is executed taking a target x ij and a mutant vector v ij , with a probability value P c between 0 and 1.…”

Section: De Algorithmmentioning

confidence: 99%

“…In terms of the optimal sizing of CMOS analog integrated circuits (ICs), it remains a challenge to accomplish target specifications and, during recent years, metaheuristics have shown their usefulness in this task. For instance, some recent mono-objective metaheuristics applied in the optimization of analog ICs can be found in [1][2][3][4][5] and some multi-objective metaheuristics can be found in [6][7][8][9]. Nevertheless, the design of ICs using CMOS technology, especially in the analog domain, remains a complex process due to the many design variables, constraints and trade-offs among them.…”

Section: Introductionmentioning

confidence: 99%

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On the Sizing of CMOS Operational Amplifiers by Applying Many-Objective Optimization Algorithms

2021

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In CMOS integrated circuit (IC) design, operational amplifiers are one of the most useful active devices to enhance applications in analog signal processing, signal conditioning and so on. However, due to the CMOS technology downscaling, along the very large number of design variables and their trade-offs, it results difficult to reach target specifications without the application of optimization methods. For this reason, this work shows the advantages of performing many-objective optimization and this algorithm is compared to the well-known mono- and multi-objective metaheuristics, which have demonstrated their usefulness in sizing CMOS ICs. Three CMOS operational transconductance amplifiers are the case study in this work; they were sized by applying mono-, multi- and many-objective algorithms. The well-known non-dominated sorting genetic algorithm version 3 (NSGA-III) and the many-objective metaheuristic-based on the R2 indicator (MOMBI-II) were applied to size CMOS amplifiers and their sized solutions were compared to mono- and multi-objective algorithms. The CMOS amplifiers were optimized considering five targets, associated to a figure of merit (FoM), differential gain, power consumption, common-mode rejection ratio and total silicon area. The designs were performed using UMC 180 nm CMOS technology. To show the advantage of applying many-objective optimization algorithms to size CMOS amplifiers, the amplifier with the best performance was used to design a fractional-order integrator based on OTA-C filters. A variation analysis considering the process, the voltage and temperature (PVT) and a Monte Carlo analysis were performed to verify design robustness. Finally, the OTA-based fractional-order integrator was used to design a fractional-order chaotic oscillator, showing good agreement between numerical and SPICE simulations.

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Section: De Algorithmmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

On the Sizing of CMOS Operational Amplifiers by Applying Many-Objective Optimization Algorithms

2021

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“…Regarding the work described in [12], the authors proposed a mono-objective metaheuristic (whale optimization algorithm) applied to the optimization of values for the aspect ratios of MOSFETs and the biasing currents of an amplifier intended for lowpower low-voltage biomedical applications. The study described [13] proposed the use of multi-objective metaheuristics with an optimization algorithm inspired by butterflies to optimize analog CMOS ICs, taking into account the performance evaluation in relation to the variations of the manufacturing process, supply voltage, and temperature (robustness analysis). However, those robustness analyses are not in the loop of the design and optimization processes of analog CMOS ICs, which can result in a considerable increase in DOCT.…”

Section: Introductionmentioning

confidence: 99%

Customized Imperialist Competitive Algorithm Methodology to Optimize Robust Miller CMOS OTAs

Galembeck¹,

Gimenez

Moreto³

2022

Electronics

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The design and optimization of the analog complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) are intrinsically complicated and depend heavily on the designer’s experience, and are associated with very long design and optimization-cycle times. In addition, in order to the analog and radiofrequency (RF) CMOS IC work suitably in practice, it is necessary to perform robustness analyses (RAs) through Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, which result in still-higher design and optimization cycle times and therefore represent the biggest bottleneck to the launching of new electronic products. In this context, this manuscript aims to present, for the first time, the use of a custom imperialist competitive algorithm (ICA) in order to reduce the design and optimization-cycle times of analog CMOS ICs. In this study, we implement some Miller CMOS operational transconductance amplifiers (OTAs) using the computational tool named iMTGSPICE, considering two different bulk CMOS IC manufacturing processes from Taiwan Semiconductor Company (TSMC) (180 nm and 65 nm nodes) and two evolutionary optimization methodologies of artificial intelligence, i.e., ICA and a genetic algorithm (GA). The main result obtained by this work shows that, by using an ICA-customized evolutionary algorithm to perform the design and optimization processes of Miller CMOS OTAs, it is possible to reduce the design and optimization-cycle times by up to 83% in relation to those implemented with the GA-customized evolutionary algorithm, achieving practically the same electrical performance.

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“…In addition, the application of sub-threshold voltage biased bulk-driven (BD) transistors has attracted considerable attention allowing the design of circuits powered by sub-0.5V voltage and rail-to-rail signal swing [4,5]. Current conveyors are flexible active building blocks that can be used for both current-mode and voltage-mode analog IC applications [6]. The CCII has the advantage of being easily realized in bipolar and CMOS technologies, as well as high linearity, and large signal bandwidth [7].…”

Section: Introductionmentioning

confidence: 99%

Bulk-driven current conveyor optimization using simulation-based method

2022

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This paper presents the optimization of a novel low-voltage (LV) and low-power (LP) bulk driven current conveyor (CCII). For the bulk-driven circuits, the transistors are biased at the subthreshold regime for LV and LP operation. In contrast, the input transistors of the differential stage are controlled from the bulk terminals to achieve a rail-to-rail input voltage range. A simulation-based technique is adapted for the optimal design of LV-LP bulk driven CCII, using the single-objective particle swarm optimization (PSO) algorithm. It is designed using CMOS 0.18 μm technology to operate at a voltage of 0.3 V and have a power consumption of 37 nW. Optimization results and also process/temperature corner results confirm the correct operation of the designed circuit.

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Efficient butterfly inspired optimization algorithm for analog circuits design

Cited by 17 publications

References 35 publications

On the Sizing of CMOS Operational Amplifiers by Applying Many-Objective Optimization Algorithms

On the Sizing of CMOS Operational Amplifiers by Applying Many-Objective Optimization Algorithms

Customized Imperialist Competitive Algorithm Methodology to Optimize Robust Miller CMOS OTAs

Bulk-driven current conveyor optimization using simulation-based method

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